i965_drv_vidoe: Encoder on Sandy Bridge

Currently it supports Intra frame
Signed-off-by: Zhou Chang <chang.zhou@intel.com>
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>

configure.ac

@@ -178,6 +178,7 @@ AC_OUTPUT([
 	i965_drv_video/shaders/mpeg2/vld/Makefile
 	i965_drv_video/shaders/render/Makefile
 	i965_drv_video/shaders/post_processing/Makefile
+	i965_drv_video/shaders/vme/Makefile
 	test/Makefile
 	test/basic/Makefile
 	test/decode/Makefile

i965_drv_video/Makefile.am

@@ -44,7 +44,10 @@ i965_drv_video_la_SOURCES =	\
 	i965_avc_hw_scoreboard.c\
 	i965_avc_ildb.c		\
 	i965_post_processing.c	\
-	gen6_mfd.c
+	gen6_mfd.c		\
+	i965_encoder.c		\
+	gen6_vme.c		\
+	gen6_mfc.c
 
 noinst_HEADERS =                \
 	object_heap.h           \
@@ -63,4 +66,7 @@ noinst_HEADERS =                \
 	i965_avc_hw_scoreboard.h\
 	i965_avc_ildb.h		\
 	i965_post_processing.h	\
-	gen6_mfd.h
+	gen6_mfd.h		\
+	i965_encoder.h		\
+	gen6_vme.h		\
+	gen6_mfc.h

i965_drv_video/gen6_mfc.h

+/*
+ * Copyright © 2010 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
+ * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
+ * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ *    Zhou Chang <chang.zhou@intel.com>
+ *
+ */
+
+#ifndef _GEN6_MFC_BCS_H_
+#define _GEN6_MFC_BCS_H_
+
+#include <xf86drm.h>
+#include <drm.h>
+#include <i915_drm.h>
+#include <intel_bufmgr.h>
+
+struct mfc_encode_state;
+
+#define MAX_MFC_REFERENCE_SURFACES        16
+#define NUM_MFC_DMV_BUFFERS				  34
+struct gen6_mfc_bcs_state 
+{
+    struct {
+        unsigned int width;
+        unsigned int height;
+        unsigned int w_pitch;
+        unsigned int h_pitch;
+    } surface_state;
+
+
+    //MFX_PIPE_BUF_ADDR_STATE
+    struct {
+        dri_bo *bo;                            	
+    } post_deblocking_output;                   		//OUTPUT: reconstructed picture                           
+    
+    struct {  
+        dri_bo *bo;							   	
+    } pre_deblocking_output;                    		//OUTPUT: reconstructed picture with deblocked                           
+
+    struct {
+        dri_bo *bo;
+    } uncompressed_picture_source;						//INPUT: original compressed image
+
+    struct {
+        dri_bo *bo;							  	
+    } intra_row_store_scratch_buffer;					//INTERNAL:
+
+    struct {
+        dri_bo *bo;								
+    } deblocking_filter_row_store_scratch_buffer;		//INTERNAL:
+
+    struct {                                    
+        VASurfaceID surface_id;                                  
+    } reference_surfaces[MAX_MFC_REFERENCE_SURFACES];	//INTERNAL: refrence surfaces
+
+    //MFX_IND_OBJ_BASE_ADDR_STATE
+    struct{
+        dri_bo *bo;
+    } mfc_indirect_mv_object;							//INPUT: the blocks' mv info
+
+    struct {
+        dri_bo *bo;
+    } mfc_indirect_pak_bse_object;						//OUTPUT: the compressed bitstream 
+
+    //MFX_BSP_BUF_BASE_ADDR_STATE
+    struct {
+        dri_bo *bo;
+    }bsd_mpc_row_store_scratch_buffer;					//INTERNAL:
+	
+    //MFX_AVC_DIRECTMODE_STATE
+    struct {
+        dri_bo *bo;
+    }direct_mv_buffers[NUM_MFC_DMV_BUFFERS];				//INTERNAL:	0-31 as input,32 and 33 as output
+};
+
+VAStatus gen6_mfc_pipeline(VADriverContextP ctx, 
+                           VAContextID context,                              
+                           struct mfc_encode_state *encode_state);
+
+#endif	/* _GEN6_MFC_BCS_H_ */

i965_drv_video/gen6_vme.h

+/*
+ * Copyright © 2009 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
+ * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
+ * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWAR
+ *
+ * Authors:
+ *    Zhou Chang <chang.zhou@intel.com>
+ *
+ */
+
+#ifndef _GEN6_MEDIA_H_
+#define _GEN6_MEDIA_H_
+
+#include <xf86drm.h>
+#include <drm.h>
+#include <i915_drm.h>
+#include <intel_bufmgr.h>
+
+
+#define MAX_INTERFACE_DESC_GEN6      32
+#define MAX_MEDIA_SURFACES_GEN6      34
+
+struct mfc_encode_state;
+
+struct gen6_media_state 
+{
+    struct {
+        dri_bo *bo;
+    } surface_state[MAX_MEDIA_SURFACES_GEN6];
+
+    struct {
+        dri_bo *bo;
+    } binding_table;
+
+    struct {
+        dri_bo *bo;
+    } idrt;  /* interface descriptor remap table */
+
+    struct {
+        dri_bo *bo;
+    } curbe;
+
+    struct {
+        unsigned int gpgpu_mode:1;
+        unsigned int max_num_threads:16;
+        unsigned int num_urb_entries:8;
+        unsigned int urb_entry_size:16;
+        unsigned int curb_size:16;
+    } vfe_state;
+
+    struct {
+        dri_bo *bo;
+    } vme_state;
+
+    struct {
+        dri_bo *bo;
+        unsigned int num_blocks;
+        unsigned int size_block; /* in bytes */
+        unsigned int pitch;
+    } vme_output;
+};
+
+VAStatus gen6_vme_media_pipeline(VADriverContextP ctx,
+                                 VAContextID context,                              
+                                 struct mfc_encode_state *encode_state);
+Bool gen6_vme_init(VADriverContextP ctx);
+Bool gen6_vme_terminate(VADriverContextP ctx);
+
+#endif /* _GEN6_MEDIA_H_ */

i965_drv_video/i965_defines.h

@@ -17,6 +17,9 @@
 #define CMD_SAMPLER_PALETTE_LOAD                CMD(3, 1, 2)
 
 #define CMD_MEDIA_STATE_POINTERS                CMD(2, 0, 0)
+#define CMD_MEDIA_VFE_STATE                     CMD(2, 0, 0)
+#define CMD_MEDIA_CURBE_LOAD                    CMD(2, 0, 1)
+#define CMD_MEDIA_INTERFACE_LOAD                CMD(2, 0, 2)
 #define CMD_MEDIA_OBJECT                        CMD(2, 1, 0)
 #define CMD_MEDIA_OBJECT_EX                     CMD(2, 1, 1)
 
@@ -54,6 +57,8 @@
 /* DW1 */
 # define CMD_CLEAR_PARAMS_DEPTH_CLEAR_VALID     (1 << 15)
 
+#define CMD_PIPE_CONTROL                        CMD(3, 2, 0)
+
 /* for GEN6+ */
 #define GEN6_3DSTATE_SAMPLER_STATE_POINTERS	CMD(3, 0, 0x02)
 # define GEN6_3DSTATE_SAMPLER_STATE_MODIFY_PS	(1 << 12)
@@ -166,6 +171,10 @@
 
 #define MFD_AVC_BSD_OBJECT                      MFX(2, 1, 1, 8)
 
+#define MFC_AVC_FQM_STATE                       MFX(2, 1, 2, 2)
+#define MFC_AVC_INSERT_OBJECT                   MFX(2, 1, 2, 8)
+#define MFC_AVC_PAK_OBJECT                      MFX(2, 1, 2, 9)
+
 #define MFX_MPEG2_PIC_STATE                     MFX(2, 3, 0, 0)
 #define MFX_MPEG2_QM_STATE                      MFX(2, 3, 0, 1)
 

i965_drv_video/i965_drv_video.h

@@ -40,6 +40,9 @@
 #include "i965_media.h"
 #include "i965_render.h"
 
+#include "gen6_vme.h"
+#include "gen6_mfc.h"
+
 #define I965_MAX_PROFILES                       11
 #define I965_MAX_ENTRYPOINTS                    5
 #define I965_MAX_CONFIG_ATTRIBUTES              10
@@ -81,17 +84,32 @@ struct decode_state
     int num_slice_datas;
 };
 
+//keeping mfc encoder's stuff here
+struct mfc_encode_state
+{
+    struct buffer_store *seq_param;
+    struct buffer_store *pic_param;
+    struct buffer_store *pic_control;
+    struct buffer_store *iq_matrix;
+    struct buffer_store *q_matrix;
+    struct buffer_store **slice_params;
+    VASurfaceID current_render_target;
+    int max_slice_params;
+    int num_slice_params;
+};
+
 struct object_context 
 {
     struct object_base base;
     VAContextID context_id;
     VAConfigID config_id;
-    VASurfaceID *render_targets;
+    VASurfaceID *render_targets;		//input->encode, output->decode
     int num_render_targets;
     int picture_width;
     int picture_height;
     int flags;
     struct decode_state decode_state;
+    struct mfc_encode_state encode_state;
 };
 
 #define SURFACE_REFERENCED      (1 << 0)
@@ -168,6 +186,8 @@ struct i965_driver_data
     struct i965_media_state media_state;
     struct i965_render_state render_state;
     void *pp_context;
+    struct gen6_media_state gen6_media_state;
+    struct gen6_mfc_bcs_state gen6_mfc_bcs_state;
 };
 
 #define NEW_CONFIG_ID() object_heap_allocate(&i965->config_heap);

i965_drv_video/i965_encoder.h

+/*
+ * Copyright © 2010 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
+ * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
+ * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ *    Zhou chang <chang.zhou@intel.com>
+ *
+ */
+
+#ifndef _GEN6_MFC_H_
+#define _GEN6_MFC_H_
+
+#include <xf86drm.h>
+#include <drm.h>
+#include <i915_drm.h>
+#include <intel_bufmgr.h>
+#include "i965_structs.h"
+#include "i965_drv_video.h"
+
+
+VAStatus i965_encoder_create_context(
+    VADriverContextP ctx,
+    VAConfigID config_id,
+    int picture_width,
+    int picture_height,
+    int flag,
+    VASurfaceID *render_targets,
+    int num_render_targets,
+    struct object_context *obj_context
+    );
+
+VAStatus i965_encoder_begin_picture(
+    VADriverContextP ctx,
+    VAContextID context,
+    VASurfaceID render_target
+    );
+
+VAStatus i965_encoder_render_picture(VADriverContextP ctx,
+                                 VAContextID context,
+                                 VABufferID *buffers,
+                                 int num_buffers
+    );
+
+VAStatus i965_encoder_end_picture(VADriverContextP ctx, 
+                              VAContextID context
+    );
+
+
+void i965_encoder_destroy_context(struct object_heap *heap, struct object_base *obj);
+
+Bool i965_encoder_init(VADriverContextP ctx);
+Bool i965_encoder_terminate(VADriverContextP ctx);
+
+#endif	/* _GEN6_MFC_H_ */
+
+

i965_drv_video/shaders/Makefile.am

-SUBDIRS = h264 mpeg2 render post_processing
+SUBDIRS = h264 mpeg2 render post_processing vme

i965_drv_video/shaders/vme/Makefile.am

+INTEL_G6B = intra_frame.g6b
+
+EXTRA_DIST = $(INTEL_G6B)
+
+if HAVE_GEN4ASM
+
+SUFFIXES = .asm .g6b
+.asm.g6b:
+	m4 $*.asm > $*.g6m && intel-gen4asm -g 6 -o $@ $*.g6m && rm $*.g6m
+
+BUILT_SOURCES= $(INTEL_G6B)
+
+clean-local:
+	-rm -f $(INTEL_G6B)
+
+endif    

i965_drv_video/shaders/vme/intra_frame.asm

+/*
+ * Copyright © <2010>, Intel Corporation.
+ *
+ * This program is licensed under the terms and conditions of the
+ * Eclipse Public License (EPL), version 1.0.  The full text of the EPL is at
+ * http://www.opensource.org/licenses/eclipse-1.0.php.
+ *
+ */
+// Modual name: IntraFrame.asm
+//
+// Make intra predition estimation for Intra frame
+//
+
+//
+//  Now, begin source code....
+//
+
+include(`vme_header.inc')
+
+/*inline input data: r5~r11*/
+mov(1) r5.20<1>:UB      r0.20<1,1,0>:UB {align1}            ;
+mov(8) m0.0<1>:UD 	r5.0<8,8,1>:UD {align1};
+mov(8) m1.0<1>:UD  	r6.0<8,8,1>:UD {align1};
+mov(8) m2.0<1>:UD  	r7.0<8,8,1>:UD {align1};
+mov(8) m3.0<1>:UD  	r8.0<8,8,1>:UD {align1};
+send(8) 0 r12 null  vme(0,0,0,2) mlen 4 rlen 1 {align1};
+
+mov(1) r9.20<1>:UB      r0.20<1,1,0>:UB {align1}            ;        
+mov(8) m0.0<1>:UD 	r9.0<8,8,1>:UD 		{align1};
+mov(1) m1.0<1>:UD	r12.0<0,1,0>:UD		{align1};		/*W0.0*/
+mov(1) m1.4<1>:UD	r12.16<0,1,0>:UD	{align1};		/*W0.4*/
+mov(1) m1.8<1>:UD	r12.20<0,1,0>:UD	{align1};		/*W0.5*/
+mov(1) m1.12<1>:UD	r12.24<0,1,0>:UD	{align1};		/*W0.6*/
+
+/* bind index 3, write 1 oword, msg type: 8(OWord Block Write) */
+send (16) 0 r13 null write(3, 0, 8, 1) mlen 2 rlen 1 {align1};
+
+mov (8) m0.0<1>:UD r0<8,8,1>:UD {align1};
+send (16) 0 acc0<1>UW null thread_spawner(0, 0, 1) mlen 1 rlen 0 {align1 EOT};
+

i965_drv_video/shaders/vme/intra_frame.g6b

+   { 0x00000001, 0x20b40231, 0x00200014, 0x00000000 },
+   { 0x00600001, 0x20000022, 0x008d00a0, 0x00000000 },
+   { 0x00600001, 0x20200022, 0x008d00c0, 0x00000000 },
+   { 0x00600001, 0x20400022, 0x008d00e0, 0x00000000 },
+   { 0x00600001, 0x20600022, 0x008d0100, 0x00000000 },
+   { 0x08600031, 0x21801cdd, 0x00000000, 0x08184000 },
+   { 0x00000001, 0x21340231, 0x00200014, 0x00000000 },
+   { 0x00600001, 0x20000022, 0x008d0120, 0x00000000 },
+   { 0x00000001, 0x20200022, 0x00000180, 0x00000000 },
+   { 0x00000001, 0x20240022, 0x00000190, 0x00000000 },
+   { 0x00000001, 0x20280022, 0x00000194, 0x00000000 },
+   { 0x00000001, 0x202c0022, 0x00000198, 0x00000000 },
+   { 0x05800031, 0x21a01cdd, 0x00000000, 0x041b0003 },
+   { 0x00600001, 0x20000022, 0x008d0000, 0x00000000 },
+   { 0x07800031, 0x24001cc8, 0x00000000, 0x82000010 },

i965_drv_video/shaders/vme/vme_header.inc

+/*
+ * Copyright © <2010>, Intel Corporation.
+ *
+ * This program is licensed under the terms and conditions of the
+ * Eclipse Public License (EPL), version 1.0.  The full text of the EPL is at
+ * http://www.opensource.org/licenses/eclipse-1.0.php.
+ *
+ */
+// Modual name: ME_header.inc
+//
+// Global symbols define
+//
+
+
+
+
+
+