If not MMU and not v6K, access to the TLS register has to be
emulated. MMU-less systems do not provide a high page for kuser
helpers.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

There is no MMU context switching on MMU-less systems.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

The __cpu_{clear|copy}_user_page functions are not defined for the
MMU-less case and therefore should not be exported.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

The patch adds the necessary ifdefs around functions that only make
sense when the MMU is enabled.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

The FSR bit 11 is not set by a memory write causing a data abort while
in Jazelle state, making the copy-on-write mechanism unusable. This
workaround marks repetitive Jazelle data aborts on the same address as
write aborts.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

Because of hardware problems, the IRQ line from the secondary GIC is
always asserted.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

Signed-off-by: Bahadir Balban <bahadir.balban@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

Signed-off-by: Bahadir Balban <bahadir.balban@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

Device driver for the SMSC LAN911x/LAN921x families embedded Ethernet
chips.
Signed-off-by: Steve Glendinning <steve.glendinning@smsc.com>
Signed-off-by: Bahadir Balban <bahadir.balban@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

RealView/EB revD platform comes with the SMSC LAN9118 Ethernet
chip. This patch allows either the smc91x or the smc911x drivers to be
used with the RealView/EB platform.
Signed-off-by: Bahadir Balban <bahadir.balban@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

Currently, Linux doesn't generate correct page tables for ARMv6 and
later cores if the cache policy is different from the default one (it
may lead to strongly ordered or shared device mappings). This patch
disallows cache policies other than writeback and the
CPU_[ID]CACHE_DISABLE options only affect the CP15 system control
register rather than the page tables.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

The auxiliary control and the L2 auxiliary control registers are
Cortex-A8 specific. They need to be removed from the generic ARMv7
support code.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

Starting with ARMv7, the cacheability attributes of the page table
walks have to be the same as the attributes of the page table
mappings, therefore inner cacheable, even if the presence of this
feature in hardware is implementation defined.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

I-cache invalidation in __new_context (the ASID-tagged VIVT I-cache
case) also flushes the branch target cache and therefore the explicit
BTAC/BTB flushing is not required.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

The cpu_architecture() function in arch/arm/kernel/setup.c only works
with cores produced by ARM Ltd. The more generic approach is to read
the ID_MMFR0 register and check for the VMSA or PMSA version
supported.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

The attached patch implements Thumb-2 application support in Linux. There
are two main changes:

- Use IFAR when handling prefetch aborts
- Handle undefined instruction traps from coprocessor instructions in Thumb
  mode
Signed-off-by: Paul Brook <paul@codesourcery.com>

This patch enables the use of the Neon extension on ARMv7 (Cortex-A8).
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

This patch adds the support for VFPv3 (the kernel currently supports
VFPv2). The main differences are 32 double registers (compared to 16)
and missing FPINST and FPINST2 registers.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

The current arch/arm/boot/compressed/head.S code only supports cores
to ARMv6 with the old CPU Id format. This patch adds support for the
new ARMv6 with the new CPU Id and ARMv7 cores that no longer have the
ARMv4 cache operations.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

We were previously using the ARMv6 operations but duplicated some of
the code because of the introduction of the new CPU barrier
instructions in ARMv7.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

This patch adds the necessary lines to the Makefile and Kconfig files for
enabling the compilation of the ARMv7 CPU support.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

ARMv7 can have VIPT, PIPT or ASID-tagged VIVT I-cache. This patch adds
the necessary invalidation of the I-cache when the ASID numbers are
re-used.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

This patch renames the old __cacheid_* macros to __cacheid_*_prev7 and adds
support for the new format.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

Starting with ARMv7, there are dedicated instruction for the ISB, DSB
and DMB barriers and there is no need to execute them as CP15
operations.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

This patch adds the Linux support for the ARMv7 cores.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

ARMv7 support code requires a valid stack for saving/restoring
registers as the whole D-cache flushing function is more complex. This
patch ensures that the SP register is not corrupted.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

In the arch/arm/boot/compressed/head.S file, the contents of the
literal pool accumulated during the relocatable code must be dumped
before reloc_end.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

Because of possible unpredictable behaviour caused by the overlapping
of sections and supersections during the initial memory setup (may
lead to two TLB entries for the same virtual address), this patch
disables the use of supersections for addresses < 4GB.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

This is useful for initial debugging and when CONFIG_DEBUG_LL is set.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

This function prints the error code returned by execve.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

Sets ARCH to arm and CROSS_COMPILE to arm-none-linux-gnueabi-.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

Presently, we check for the minimum ARM architecture that we're
building for to determine whether we need ASID support.  This is
wrong - if we're going to support a range of CPUs which include
ARMv6 or higher, we need the ASID.

Convert the checks to use a new configuration symbol, and arrange
for ARMv6 and higher CPU entries to select it.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

Fix the undeclared symbols sparse is warning about.

arch/arm/nwfpe/softfloat.c:1727:7: warning: symbol 'float64_to_uint32' was not declared. Should it be static?
arch/arm/nwfpe/softfloat.c:1753:7: warning: symbol 'float64_to_uint32_round_to_zero' was not declared. Should it be static?
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

Fix lockdep warnings, caused by 'set_affinity' being called without
the correct locks taken and local interrupts disabled:

=================================
[ INFO: inconsistent lock state ]
2.6.22-rc2 #1
---------------------------------
inconsistent {in-hardirq-W} -> {hardirq-on-W} usage.
swapper/1 [HC0[0]:SC0[0]:HE1:SE1] takes:
(irq_controller_lock){++..}, at: [<c002be50>] gic_set_cpu+0x60/0xa0
{in-hardirq-W} state was registered at:
 [<c005d9a8>] lock_acquire+0x58/0x6c
 [<c0233068>] _spin_lock+0x40/0x50
 [<c002c020>] gic_mask_irq+0x2c/0x6c
 [<c0069c64>] handle_level_irq+0x11c/0x14c
 [<c0020060>] asm_do_IRQ+0x60/0x84
 [<c0020d2c>] __irq_svc+0x4c/0xc0
 [<c000ed84>] __alloc_bootmem_nopanic+0x74/0x88
 [<c000edb0>] __alloc_bootmem+0x18/0x3c
 [<c000fa00>] alloc_large_system_hash+0x16c/0x200
 [<c00108dc>] inode_init_early+0x5c/0xa4
 [<c00106dc>] vfs_caches_init_early+0x24/0xa0
 [<c0008e54>] start_kernel+0x220/0x2fc
 [<00008078>] 0x8078
irq event stamp: 88438
hardirqs last  enabled at (88438): [<c0020dc0>] preempt_return+0x20/0x2c
hardirqs last disabled at (88436): [<c00417bc>] __do_softirq+0xb0/0x138
softirqs last  enabled at (88437): [<c0041810>] __do_softirq+0x104/0x138
softirqs last disabled at (88428): [<c0041d9c>] irq_exit+0x68/0x7c

other info that might help us debug this:
no locks held by swapper/1.

stack backtrace:
[<c0025ecc>] (dump_stack+0x0/0x14) from [<c005b1e4>] (print_usage_bug+0x138/0x168)
[<c005b0ac>] (print_usage_bug+0x0/0x168) from [<c005be80>] (mark_lock+0x484/0x6a0)
[<c005b9fc>] (mark_lock+0x0/0x6a0) from [<c005cc48>] (__lock_acquire+0x3c0/0x10c8)
[<c005c888>] (__lock_acquire+0x0/0x10c8) from [<c005d9a8>] (lock_acquire+0x58/0x6c)
[<c005d950>] (lock_acquire+0x0/0x6c) from [<c0233068>] (_spin_lock+0x40/0x50)
[<c0233028>] (_spin_lock+0x0/0x50) from [<c002be50>] (gic_set_cpu+0x60/0xa0)
[<c002bdf0>] (gic_set_cpu+0x0/0xa0) from [<c01b04cc>] (em_route_irq+0x38/0x40)
[<c01b0494>] (em_route_irq+0x0/0x40) from [<c01b04ec>] (em_setup+0x18/0xa4)
[<c01b04d4>] (em_setup+0x0/0xa4) from [<c001570c>] (oprofile_arch_init+0x24/0xe8)
[<c00156e8>] (oprofile_arch_init+0x0/0xe8) from [<c0015640>] (oprofile_init+0x1c/0x64)
[<c0015624>] (oprofile_init+0x0/0x64) from [<c0008a20>] (kernel_init+0x154/0x368)
[<c00088cc>] (kernel_init+0x0/0x368) from [<c003ef34>] (do_exit+0x0/0x904)
oprofile: using arm/mpcore
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

We don't need valid_phys_addr_range() or valid_mmap_phys_addr_range()
for the !CONFIG_MMU case.
Signed-off-by: Greg Ungerer <gerg@uclinux.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

No need for the cascade irq function to have a "fastcall" annotation.
Fix the range checking for valid IRQ numbers - comparing the value
returned by the GIC with NR_IRQS is meaningless since we translate
the GIC irq number to a Linux IRQ number afterwards.

Check the GIC returned IRQ number is within limits first, then add
the IRQ offset, and only then compare with NR_IRQS.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

Branches in the ARM architecture are restricted to a range of +/- 32MB.
However, the code in .../arch/arm/kernel/module.c::apply_relocate() was
checking offset against a range of +/- 64MB.
Signed-off-by: Kevin Welton <Kevin.Welton@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>