This patch is a workaround for the 364296 ARM1136 r0pX errata
(possible cache data corruption with hit-under-miss enabled). It sets
the undocumented bit 31 in the auxiliary control register and the FI bit in
the control register, thus disabling hit-under-miss without putting the
processor into full low interrupt latency mode.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

When running Linux in non-secure mode (on ARM1176 for example),
depending on the CP15 secure configuration register, the CPSR.F bit
(6) might only be modified from the secure mode. However, the
valid_user_regs() function checks for this bit being cleared. With
commit a6c61e9d, a SIGSEGV is forced in handle_signal() if the user
registers are not considered valid.

The patch also ensures that the CPSR.A bit is cleared and the USR mode
is set if the CPU does not support the 26bit user mode.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

The patch moves the HWCAP definitions and the extern elf_hwcap
declaration to the hwcap.h header file.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

The background operations of the L2x0 cache controllers are aborted if
another operation is issued on the same or different core. This patch
protects the maintenance operation issuing/polling with a spinlock.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

Starting with ARMv7-A, conditional execution of undefined instructions
can trigger an exception even if the condition check fails. This patch
modifies the NWFPE support to check the condition before emulating the
instruction.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

This is to avoid a compiler warning for overriding the built-in "putc"
function.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

MMU option is now selectable.
Signed-off-by: Hyok S. Choi <hyok.choi@samsung.com>

The patch below adds ARM ptrace functions to get the process load address.
This is required for useful userspace debugging on mmuless systems.  These
values are obtained by reading magic offsets with PTRACE_PEEKUSR, as on other
nommu targets. I picked arbitrary large values for the offsets.
Signed-off-by: Paul Brook <paul@codesourcery.com>

This patch redefines the IO_ADDRESS macro.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

This patch redefines the IO_ADDRESS macro in
include/asm-arm/hardware.h.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

The patch adds the empty arch_{enter,leave,flush}_lazy_{mmu,cpu}_mode
macros to pgtable-nommu.h
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

This patch adds the necessary ifdef's to the proc-v7.S code and
defines the v7wbi_tlb_fns macro in pgtable-nommu.h
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

With this patch, Kconfig only selects CPU_HAS_ASID for the MMU
case. It also corrects the typo in the v6wbi_tlb_fns definition in
pgtable-nommu.h.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

If not MMU and not v6K, access to the TLS register has to be
emulated. MMU-less systems do not provide a high page for kuser
helpers.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

There is no MMU context switching on MMU-less systems.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

The __cpu_{clear|copy}_user_page functions are not defined for the
MMU-less case and therefore should not be exported.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

The patch adds the necessary ifdefs around functions that only make
sense when the MMU is enabled.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

The FSR bit 11 is not set by a memory write causing a data abort while
in Jazelle state, making the copy-on-write mechanism unusable. This
workaround marks repetitive Jazelle data aborts on the same address as
write aborts.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

Because of hardware problems, the IRQ line from the secondary GIC is
always asserted.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

Signed-off-by: Bahadir Balban <bahadir.balban@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

Signed-off-by: Bahadir Balban <bahadir.balban@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

Device driver for the SMSC LAN911x/LAN921x families embedded Ethernet
chips.
Signed-off-by: Steve Glendinning <steve.glendinning@smsc.com>
Signed-off-by: Bahadir Balban <bahadir.balban@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

RealView/EB revD platform comes with the SMSC LAN9118 Ethernet
chip. This patch allows either the smc91x or the smc911x drivers to be
used with the RealView/EB platform.
Signed-off-by: Bahadir Balban <bahadir.balban@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

Currently, Linux doesn't generate correct page tables for ARMv6 and
later cores if the cache policy is different from the default one (it
may lead to strongly ordered or shared device mappings). This patch
disallows cache policies other than writeback and the
CPU_[ID]CACHE_DISABLE options only affect the CP15 system control
register rather than the page tables.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

The auxiliary control and the L2 auxiliary control registers are
Cortex-A8 specific. They need to be removed from the generic ARMv7
support code.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

Starting with ARMv7, the cacheability attributes of the page table
walks have to be the same as the attributes of the page table
mappings, therefore inner cacheable, even if the presence of this
feature in hardware is implementation defined.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

I-cache invalidation in __new_context (the ASID-tagged VIVT I-cache
case) also flushes the branch target cache and therefore the explicit
BTAC/BTB flushing is not required.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

The cpu_architecture() function in arch/arm/kernel/setup.c only works
with cores produced by ARM Ltd. The more generic approach is to read
the ID_MMFR0 register and check for the VMSA or PMSA version
supported.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

The attached patch implements Thumb-2 application support in Linux. There
are two main changes:

- Use IFAR when handling prefetch aborts
- Handle undefined instruction traps from coprocessor instructions in Thumb
  mode
Signed-off-by: Paul Brook <paul@codesourcery.com>

This patch enables the use of the Neon extension on ARMv7 (Cortex-A8).
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

This patch adds the support for VFPv3 (the kernel currently supports
VFPv2). The main differences are 32 double registers (compared to 16)
and missing FPINST and FPINST2 registers.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

The current arch/arm/boot/compressed/head.S code only supports cores
to ARMv6 with the old CPU Id format. This patch adds support for the
new ARMv6 with the new CPU Id and ARMv7 cores that no longer have the
ARMv4 cache operations.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

We were previously using the ARMv6 operations but duplicated some of
the code because of the introduction of the new CPU barrier
instructions in ARMv7.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

This patch adds the necessary lines to the Makefile and Kconfig files for
enabling the compilation of the ARMv7 CPU support.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

ARMv7 can have VIPT, PIPT or ASID-tagged VIVT I-cache. This patch adds
the necessary invalidation of the I-cache when the ASID numbers are
re-used.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

This patch renames the old __cacheid_* macros to __cacheid_*_prev7 and adds
support for the new format.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

Starting with ARMv7, there are dedicated instruction for the ISB, DSB
and DMB barriers and there is no need to execute them as CP15
operations.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>