- 19 Jul, 2007 23 commits
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Catalin Marinas authored
This patch adds the ARM/Thumb-2 unified support for the arch/arm/boot/* files. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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Catalin Marinas authored
This patch modifies the VFP files for the ARM/Thumb-2 unified assembler syntax. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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Catalin Marinas authored
This patch adds the ARM/Thumb-2 unified support the Integrator boards. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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Catalin Marinas authored
This patch adds ARM/Thumb-2 unified support for spinlocks, mutexes, semaphores and the atomic operations. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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Catalin Marinas authored
This patch adds the ARM/Thumb-2 unified support for the arch/arm/lib/* files. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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Catalin Marinas authored
This patch adds the ARM/Thumb-2 unified support to the arch/arm/mm/* files. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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Catalin Marinas authored
This patch implements the ARM/Thumb-2 unified kernel start-up and exception handling code. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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Catalin Marinas authored
This patch adds various C and assembler macros that help with using the unified assembler syntax for compiling files to either ARM or Thumb-2 modes. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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Catalin Marinas authored
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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Harry Fearnhamm authored
According to the ARM11MPCore Erratum 351422 (r0p0), under extremely rare conditions, in an MPCore node consisting of at least 3 CPUs, two CPUs trying to perform a STREX to data on the same shared cache line can enter a livelock situation. This patch adds variable spinning time to the locking routines. Signed-off-by: Harry Fearnhamm <Harry.Fearnhamm@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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Catalin Marinas authored
Errata 411920 - Invalidation of the Instruction Cache operation can fail. This Errata is present in 1136, 1156 and 1176. It does not affect the MPCore. This patch implements the ARM Ltd recommended workaround. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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Catalin Marinas authored
This patch is a workaround for the 364296 ARM1136 r0pX errata (possible cache data corruption with hit-under-miss enabled). It sets the undocumented bit 31 in the auxiliary control register and the FI bit in the control register, thus disabling hit-under-miss without putting the processor into full low interrupt latency mode. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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Catalin Marinas authored
When running Linux in non-secure mode (on ARM1176 for example), depending on the CP15 secure configuration register, the CPSR.F bit (6) might only be modified from the secure mode. However, the valid_user_regs() function checks for this bit being cleared. With commit a6c61e9d, a SIGSEGV is forced in handle_signal() if the user registers are not considered valid. The patch also ensures that the CPSR.A bit is cleared and the USR mode is set if the CPU does not support the 26bit user mode. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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Catalin Marinas authored
The patch moves the HWCAP definitions and the extern elf_hwcap declaration to the hwcap.h header file. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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Catalin Marinas authored
The background operations of the L2x0 cache controllers are aborted if another operation is issued on the same or different core. This patch protects the maintenance operation issuing/polling with a spinlock. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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Catalin Marinas authored
Starting with ARMv7-A, conditional execution of undefined instructions can trigger an exception even if the condition check fails. This patch modifies the NWFPE support to check the condition before emulating the instruction. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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Catalin Marinas authored
This is to avoid a compiler warning for overriding the built-in "putc" function. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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Hyok S. Choi authored
MMU option is now selectable. Signed-off-by: Hyok S. Choi <hyok.choi@samsung.com>
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Paul Brook authored
The patch below adds ARM ptrace functions to get the process load address. This is required for useful userspace debugging on mmuless systems. These values are obtained by reading magic offsets with PTRACE_PEEKUSR, as on other nommu targets. I picked arbitrary large values for the offsets. Signed-off-by: Paul Brook <paul@codesourcery.com>
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Catalin Marinas authored
This patch redefines the IO_ADDRESS macro. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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Catalin Marinas authored
This patch redefines the IO_ADDRESS macro in include/asm-arm/hardware.h. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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Catalin Marinas authored
The patch adds the empty arch_{enter,leave,flush}_lazy_{mmu,cpu}_mode macros to pgtable-nommu.h Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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Catalin Marinas authored
This patch adds the necessary ifdef's to the proc-v7.S code and defines the v7wbi_tlb_fns macro in pgtable-nommu.h Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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- 18 Jul, 2007 15 commits
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Catalin Marinas authored
With this patch, Kconfig only selects CPU_HAS_ASID for the MMU case. It also corrects the typo in the v6wbi_tlb_fns definition in pgtable-nommu.h. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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Catalin Marinas authored
If not MMU and not v6K, access to the TLS register has to be emulated. MMU-less systems do not provide a high page for kuser helpers. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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Catalin Marinas authored
There is no MMU context switching on MMU-less systems. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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Catalin Marinas authored
The __cpu_{clear|copy}_user_page functions are not defined for the MMU-less case and therefore should not be exported. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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Catalin Marinas authored
The patch adds the necessary ifdefs around functions that only make sense when the MMU is enabled. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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Catalin Marinas authored
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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Catalin Marinas authored
The FSR bit 11 is not set by a memory write causing a data abort while in Jazelle state, making the copy-on-write mechanism unusable. This workaround marks repetitive Jazelle data aborts on the same address as write aborts. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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Catalin Marinas authored
Because of hardware problems, the IRQ line from the secondary GIC is always asserted. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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Bahadir Balban authored
Signed-off-by: Bahadir Balban <bahadir.balban@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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Bahadir Balban authored
Signed-off-by: Bahadir Balban <bahadir.balban@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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Steve Glendinning authored
Device driver for the SMSC LAN911x/LAN921x families embedded Ethernet chips. Signed-off-by: Steve Glendinning <steve.glendinning@smsc.com> Signed-off-by: Bahadir Balban <bahadir.balban@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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Bahadir Balban authored
RealView/EB revD platform comes with the SMSC LAN9118 Ethernet chip. This patch allows either the smc91x or the smc911x drivers to be used with the RealView/EB platform. Signed-off-by: Bahadir Balban <bahadir.balban@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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Bahadir Balban authored
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Catalin Marinas authored
Currently, Linux doesn't generate correct page tables for ARMv6 and later cores if the cache policy is different from the default one (it may lead to strongly ordered or shared device mappings). This patch disallows cache policies other than writeback and the CPU_[ID]CACHE_DISABLE options only affect the CP15 system control register rather than the page tables. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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Catalin Marinas authored
The auxiliary control and the L2 auxiliary control registers are Cortex-A8 specific. They need to be removed from the generic ARMv7 support code. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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- 13 Jul, 2007 1 commit
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Catalin Marinas authored
Starting with ARMv7, the cacheability attributes of the page table walks have to be the same as the attributes of the page table mappings, therefore inner cacheable, even if the presence of this feature in hardware is implementation defined. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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- 09 Jul, 2007 1 commit
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Catalin Marinas authored
I-cache invalidation in __new_context (the ASID-tagged VIVT I-cache case) also flushes the branch target cache and therefore the explicit BTAC/BTB flushing is not required. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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