Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

The current ASID allocation algorithm doesn't ensure the notification
of the other CPUs when the ASID rolls over. This may lead to two
processes using the same ASID (but different generation) or multiple
threads of the same process using different ASIDs.

This patch adds the broadcasting of the ASID rollover event to the
other CPUs. To avoid a race on multiple CPUs modifying "cpu_last_asid"
during the handling of the broadcast, the ASID numbering now starts at
"smp_processor_id() + 1". At rollover, the cpu_last_asid will be set
to NR_CPUS.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

This patch adds the workaround for the 484863 L220 erratum. The
writing of the L220 registers is done with a SWP rather than STR
instruction.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

This patch is a workaround for the 460075 Cortex-A8 (r2p0) erratum. It
configures the L2 cache auxiliary control register so that the Write
Allocate mode for the L2 cache is disabled.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

This patch adds a workaround for the 458692 Cortex-A8 (r2p0)
erratum. It sets the corresponding bits in the auxiliary control
register so that the PLD instruction becomes a NOP.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

This patch adds the workaround for the 430973 Cortex-A8 (r1p0)
erratum. The BTAC/BTB is now flushed at every context switch.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

According to the ARM11MPCore Erratum 351422 (r0p0), under extremely
rare conditions, in an MPCore node consisting of at least 3 CPUs, two
CPUs trying to perform a STREX to data on the same shared cache line
can enter a livelock situation. This patch adds variable spinning time
to the locking routines.
Signed-off-by: Harry Fearnhamm <Harry.Fearnhamm@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

Errata 411920 - Invalidation of the Instruction Cache operation can
fail. This Errata is present in 1136, 1156 and 1176. It does not
affect the MPCore. This patch implements the ARM Ltd recommended
workaround.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

This patch is a workaround for the 364296 ARM1136 r0pX errata
(possible cache data corruption with hit-under-miss enabled). It sets
the undocumented bit 31 in the auxiliary control register and the FI bit in
the control register, thus disabling hit-under-miss without putting the
processor into full low interrupt latency mode.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

There are some hardware-related issues on RealView EB and the interrupt
controller cannot cope with polling its registers.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

Otherwise, the caches can become uncoherent between cores.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

The FSR bit 11 is not set by a memory write causing a data abort while
in Jazelle state, making the copy-on-write mechanism unusable. This
workaround marks repetitive Jazelle data aborts on the same address as
write aborts.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

This patch adds the I-cache invalidation in update_mmu_cache if the
corresponding vma is marked as executable. It also invalidates the
I-cache if a thread migrates to a CPU it never ran on.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

The patch adds CLREX (or a dummy STREX) to the vector stub and removes
it from the __switch_to function. This allows the atomic_set to be a
simple STR instruction.

Linux currently clears the exclusive monitor at every context switch,
allowing threads to use plain STR for atomic store
operations. However, this is not enough for atomic operations in
signal handler. The patch fixes this case as well.

Note that for the SMP case, plain STR clears the state of the global
exclusive monitor. The effect of an STR on the local exclusive monitor
is implementation defined and therefore a CLREX is needed at exception
taking.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

This patch adds the necessary entries to the Makefile and Kconfig
files for building the Thumb-2 kernel.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

This patch sets bit 30 in the CP15 system control register so that the
exceptions are handled in Thumb mode when the MMU is disabled.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

This patch adds the ARM/Thumb-2 unified support the RealView boards.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

This patch adds the ARM/Thumb-2 unified support the Integrator boards.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

This patch adds the ARM/Thumb-2 unified support for the
arch/arm/boot/* files.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

This patch modifies the VFP files for the ARM/Thumb-2 unified
assembler syntax.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

This patch adds ARM/Thumb-2 unified support for spinlocks, mutexes,
semaphores and the atomic operations.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

This patch adds the ARM/Thumb-2 unified support for the arch/arm/lib/*
files.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

This patch adds the ARM/Thumb-2 unified support to the arch/arm/mm/*
files.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

This patch implements the ARM/Thumb-2 unified kernel start-up and
exception handling code.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

This patch adds various C and assembler macros that help with using
the unified assembler syntax for compiling files to either ARM or
Thumb-2 modes.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

This declaration specifies the "function" type for various assembly
functions, needed for generating the correct branch instructions in
Thumb-2.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

By default, this option was selected by the platform Kconfig. This
patch adds "depends on" to L2X0 so that it can be enabled/disabled
manually.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

This patch enables the building of Linux for the PB1176 platform.
Signed-off-by: Bahadir Balban <bahadir.balban@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

This patch adds the UART0 base address detection in uncompress.h.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

The UART0 address is different on PB1176 from EB or PB11MPCore. This
patch adds the necessary #ifdef's to this file. The disadvantage is
that enabling CONFIG_DEBUG_LL will work properly on PB1176 if only
this platform is enabled.
Signed-off-by: Bahadir Balban <bahadir.balban@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

This patch adds the base files for the PB1176 platform support.
Signed-off-by: Bahadir Balban <bahadir.balban@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

This patch adds the resource and device definitions for the compact
flash.
Signed-off-by: Bahadir Balban <bahadir.balban@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

This patch adds the PB11MPCore support to the corresponding Kconfig
and Makefile to enable building.
Signed-off-by: Bahadir Balban <bahadir.balban@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

This patch adds the UART address detection in uncompress.h for the
PB11MPCore platform.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

This patch adds the initialisation calls for the SMP support on the
PB11MPCore platform.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

This patch adds the base files for the PB11MPCore platform support.
Signed-off-by: Bahadir Balban <bahadir.balban@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

This patch changes the IO_ADDRESS macro for the RealView platforms to
accomodate a wider range of physical addresses on PB11MPCore.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

This patch changes the CPU_V7 configuration dependency to allow
MACH_REALVIEW_EB.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

The upcoming PB11MPCore and PB1176 have different memory maps and some
of the definitions in platform.h are no longer common. This patch
moves them to the board-eb.h file and updates their usage in
realview_eb.c.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>