ARMv7 support code requires a valid stack for saving/restoring
registers as the whole D-cache flushing function is more complex. This
patch ensures that the SP register is not corrupted.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

Because of possible unpredictable behaviour caused by the overlapping
of sections and supersections during the initial memory setup (may
lead to two TLB entries for the same virtual address), this patch
disables the use of supersections for addresses < 4GB.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

This patch enables the L220 on the RealView/EB MPCore platform.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

This patch adds the support for the L210/L220 (outer) cache
controller. The cache range operations are done by index/way since L2
cache controller only accepts physical addresses.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

Other platforms other than SMP may have an outer cache.  For these, we
also need to mark the page table walks outer cacheable.  Since marking
the walks always outer cacheable apparantly has no side effects, we
might as well always mark them so.

However, we continue to only mark PTWs shared if we have SMP enabled.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

The outer cache can be L2 as on RealView/EB MPCore platform or even L3
or further on ARMv7 cores. This patch adds the generic support for
flushing the outer cache in the DMA operations.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

Currently, the mb() is defined as a DMB operation on ARMv6, even for
UP systems. This patch defines mb() as a compiler barrier only. For
the SMP case, the smp_* variants should be used anyway and the patch
defines them as DMB.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

According to ARM ARM, changes to the CP15 registers are only
guaranteed to be visible after an Instruction Synchronization Barrier
(ISB). This patch adds the ISB at the end of set_cr and
set_copro_access functions and also moves them further down in the
file, below the isb macro definition.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

Starting with ARMv6, accesses to strongly ordered memory are not
guaranteed to complete before a subsequent instruction modifying the
interrupt mask in CPSR. This can cause potential problems with masking
or acknowledging an IRQ at the device or interrupt controller level
followed by a local_irq_enable or local_irq_restore (see B2.4.3 in ARM
ARM revI). This patch adds a DSB after masking the interrupts at the
interrupt controller level to ensure that the strongly ordered memory
access was completed.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

The architecture specification states that TLB operations are
guaranteed to be complete only after the execution of a DSB (Data
Synchronisation Barrier, former Data Write Barrier or Drain Write
Buffer).
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

The ARM Architecture Reference Manual specifies that a prefetch flush
is needed after changing the DACR register (chapter B2.7.6).
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

On newer architectures (ARMv6, ARMv7), the depth of the prefetch and
branch prediction is implementation defined and there is a small risk
of wrong ASID tagging when changing TTBR0 before setting the new
context id. The recommended solution is to set a reserved ASID during
TTBR changing. This patch reserves ASID 0.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

There are three barriers - ISB, DMB and DSB for different
scenarious. This patch adds their definitions in the system.h file.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

The current lazy saving of the VFP registers is no longer possible
with thread migration on SMP. This patch implements a per-CPU
vfp-state pointer and the saving of the VFP registers at every context
switch. The registers restoring is still performed in a lazy way.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

Otherwise, the caches can become uncoherent between cores.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

RealView/EB MPCore revB and revC contains r0p0 silicon, which needs
this workaround.
Signed-off-by: Harry Fearnhamm <Harry.Fearnhamm@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

Device driver for the SMSC LAN911x/LAN921x families embedded Ethernet
chips.
Signed-off-by: Steve Glendinning <steve.glendinning@smsc.com>
Signed-off-by: Bahadir Balban <bahadir.balban@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

RealView/EB revD platform comes with the SMSC LAN9118 Ethernet
chip. This patch allows either the smc91x or the smc911x drivers to be
used with the RealView/EB platform.
Signed-off-by: Bahadir Balban <bahadir.balban@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

In some situations, the pen_release store in platform_secondary_init()
may stay forever in the write buffer while the CPU is waiting on the
boot_lock to be released in boot_secondary(). The primary CPU could
never see the pen_release update without the barriers.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

The kernel originally supported revB only. This patch enables revC by
default and adds a config option for building the kernel for the revB
platform.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

This patch adds the registration of the secondary GIC on the
baseboard, together with the IRQ chaining setup.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

The current implementation only assumes one GIC to be present in the
system. However, there are platforms with more than one cascaded interrupt
controllers (RealView/EB MPCore for example).
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

Errata 411920 - Invalidation of the Instruction Cache operation can
fail. This Errata is present in 1136, 1156 and 1176. It does not
affect the MPCore. This patch implements the ARM Ltd recommended
workaround.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

This patch is a workaround for the 364296 ARM1136 r0pX errata
(possible cache data corruption with hit-under-miss enabled). It sets
the undocumented bit 31 in the auxiliary control register and the FI bit in
the control register, thus disabling hit-under-miss without putting the
processor into full low interrupt latency mode.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

Supersections do not have a field for the domain and it is always
0. This patch prevents the creation of supersections during ioremap
when DOMAIN_IO is not zero (i.e. !defined(CONFIG_IO_36)).
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

This is useful for initial debugging and when CONFIG_DEBUG_LL is set.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

This function prints the error code returned by execve.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

Sets ARCH to arm and CROSS_COMPILE to arm-none-linux-gnueabi-.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

Using console=ttyAM1 or console=ttyAMA1 resulted in an oops during
boot due to trying to drive the console before that port had been
registered.  Fix this by checking whether the port is present before
allowing console setup to proceed.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

Current sched_clock() implementations on ARM cause unbootable kernels
with PRINTK_TIME support enabled.  To avoid this, provide a basic
printk_clock() implementation which avoids sched_clock() being called
before the page tables have been set up.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

When we install the handlers for context switching, we must enable
VFP on all CPU cores, otherwise undefined (and random) effects
occur.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

If PG_dcache_dirty is set for a page, we need to flush the source page
before performing any copypage operation using a different virtual address.

This fixes the copypage implementations for XScale, StrongARM and ARMv6.

This patch fixes segmentation faults seen in the dynamic linker under
the usage patterns in glibc 2.4/2.5.
Signed-off-by: Richard Purdie <rpurdie@rpsys.net>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

Move adjust_cr() into arch/arm/mm/mmu.c, and move irqflags.h to
a more appropriate place in the header file.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

We need to ensure that the area size is page aligned so that
remap_area_pte() doesn't increment the address past the end of
the desired area.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

Add:
  sys_unshare
  sys_set_robust_list
  sys_get_robust_list
  sys_splice
  sys_arm_sync_file_range
  sys_tee
  sys_vmsplice
  sys_move_pages
  sys_getcpu

Special note about sys_arm_sync_file_range(), which is implemented as:

asmlinkage long sys_arm_sync_file_range(int fd, unsigned int flags,
                                        loff_t offset, loff_t nbytes)
{
        return sys_sync_file_range(fd, offset, nbytes, flags);
}

We can't export sys_sync_file_range() directly on ARM because the
argument list someone picked does not fit in the available registers.
Would be nice if... there was an arch maintainer review mechanism for
new syscalls before they hit the kernel.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

i.MX needs to tweak the control register to support CPU frequency
scaling.  Rather than have folk blindly try and change the control
register by writing to it and then wondering why it doesn't work,
provide a method (which is safe for UP only, and therefore only
available for UP) to achieve this.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

 optimization

The gcc manual says:

|`-fdelete-null-pointer-checks'
|     Use global dataflow analysis to identify and eliminate useless
|     checks for null pointers.  The compiler assumes that dereferencing
|     a null pointer would have halted the program.  If a pointer is
|     checked after it has already been dereferenced, it cannot be null.
|     Enabled at levels `-O2', `-O3', `-Os'.

Now the problem can be seen with this test case:

#include <linux/prefetch.h>
extern void bar(char *x);
void foo(char *x)
{
	prefetch(x);
	if (x)
		bar(x);
}

Because the constraint to the inline asm used in the prefetch() macro is
a memory operand, gcc assumes that the asm code does dereference the
pointer and the delete-null-pointer-checks optimization kicks in.
Inspection of generated assembly for the above example shows that bar()
is indeed called unconditionally without any test on the value of x.

Of course in the prefetch case there is no real dereference and it
cannot be assumed that a null pointer would have been caught at that
point. This causes kernel oopses with constructs like
hlist_for_each_entry() where the list's 'next' content is prefetched
before the pointer is tested against NULL, and only when gcc feels like
applying this optimization which doesn't happen all the time with more
complex code.

It appears that the way to prevent delete-null-pointer-checks
optimization to occur in this case is to make prefetch() into a static
inline function instead of a macro. At least this is what is done on
x86_64 where a similar inline asm memory operand is used (I presume they
would have seen the same problem if it didn't work) and resulting code
for the above example confirms that.

An alternative would consist of replacing the memory operand by a
register operand containing the pointer, and use the addressing mode
explicitly in the asm template. But that would be less optimal than an
offsettable memory reference.
Signed-off-by: Nicolas Pitre <nico@cam.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

Later glibc requires the *at syscalls.  Add them.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

Don't set HWCAP_VFP in the processor support file; not only does it
depend on the processor features, but it also depends on the support
code being present.  Therefore, only set it if the support code
detects that we have a VFP coprocessor attached.

Also, move the VFP handling of the coprocessor access register into
the VFP support code.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>