Commit 4bc47649 authored by Catalin Marinas's avatar Catalin Marinas

Add support for the RealView/EB MPCore revC platform

The kernel originally supported revB only. This patch enables revC by
default and adds a config option for building the kernel for the revB
platform.
Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
parent 7c43fa87
......@@ -16,4 +16,14 @@ config REALVIEW_MPCORE
kernel built with this option enabled is not compatible with
other tiles.
config REALVIEW_MPCORE_REVB
bool "Support MPcore RevB tile"
depends on REALVIEW_MPCORE
default n
help
Enable support for the MPCore RevB tile on the Realview platform.
Since there are device address differences, a
kernel built with this option enabled is not compatible with
other tiles.
endmenu
......@@ -152,9 +152,9 @@ static void __init gic_init_irq(void)
#ifdef CONFIG_REALVIEW_MPCORE
unsigned int pldctrl;
writel(0x0000a05f, __io_address(REALVIEW_SYS_LOCK));
pldctrl = readl(__io_address(REALVIEW_SYS_BASE) + 0xd8);
pldctrl = readl(__io_address(REALVIEW_SYS_BASE) + REALVIEW_MPCORE_SYS_PLD_CTRL1);
pldctrl |= 0x00800000; /* New irq mode */
writel(pldctrl, __io_address(REALVIEW_SYS_BASE) + 0xd8);
writel(pldctrl, __io_address(REALVIEW_SYS_BASE) + REALVIEW_MPCORE_SYS_PLD_CTRL1);
writel(0x00000000, __io_address(REALVIEW_SYS_LOCK));
#endif
gic_dist_init(0, __io_address(REALVIEW_GIC_DIST_BASE), 29);
......
......@@ -13,11 +13,14 @@
#include <linux/linkage.h>
#include <asm/assembler.h>
#include <asm/asm-offsets.h>
#include <asm/hardware/arm_scu.h>
#include <asm/elf.h>
#include <asm/pgtable-hwdef.h>
#include <asm/pgtable.h>
#ifdef CONFIG_SMP
#include <asm/hardware/arm_scu.h>
#endif
#include "proc-macros.S"
#define D_CACHE_LINE_SIZE 32
......@@ -181,8 +184,7 @@ __v6_setup:
/* Set up the SCU on core 0 only */
mrc p15, 0, r0, c0, c0, 5 @ CPU core number
ands r0, r0, #15
moveq r0, #0x10000000 @ SCU_BASE
orreq r0, r0, #0x00100000
ldreq r0, =SCU_BASE
ldreq r5, [r0, #SCU_CTRL]
orreq r5, r5, #1
streq r5, [r0, #SCU_CTRL]
......
......@@ -26,7 +26,7 @@
#include <asm/arch/platform.h>
/* macro to get at IO space when running virtually */
#define IO_ADDRESS(x) (((x) & 0x0fffffff) + (((x) >> 4) & 0x0f000000) + 0xf0000000)
#define IO_ADDRESS(x) ((((x) & 0x0effffff) | (((x) >> 4) & 0x0f000000)) + 0xf0000000)
#define __io_address(n) __io(IO_ADDRESS(n))
#endif
......@@ -207,11 +207,21 @@
#define REALVIEW_GIC_CPU_BASE 0x10040000 /* Generic interrupt controller CPU interface */
#define REALVIEW_GIC_DIST_BASE 0x10041000 /* Generic interrupt controller distributor */
#else
#ifdef CONFIG_REALVIEW_MPCORE_REVB
#define REALVIEW_MPCORE_SCU_BASE 0x10100000 /* SCU registers */
#define REALVIEW_GIC_CPU_BASE 0x10100100 /* Generic interrupt controller CPU interface */
#define REALVIEW_TWD_BASE 0x10100700
#define REALVIEW_TWD_SIZE 0x00000100
#define REALVIEW_GIC_DIST_BASE 0x10101000 /* Generic interrupt controller distributor */
#define REALVIEW_MPCORE_SYS_PLD_CTRL1 0xD8 /* Register offset for MPCore sysctl */
#else
#define REALVIEW_MPCORE_SCU_BASE 0x1F000000 /* SCU registers */
#define REALVIEW_GIC_CPU_BASE 0x1F000100 /* Generic interrupt controller CPU interface */
#define REALVIEW_TWD_BASE 0x1F000700
#define REALVIEW_TWD_SIZE 0x00000100
#define REALVIEW_GIC_DIST_BASE 0x1F001000 /* Generic interrupt controller distributor */
#define REALVIEW_MPCORE_SYS_PLD_CTRL1 0x74 /* Register offset for MPCore sysctl */
#endif
#define REALVIEW_GIC1_CPU_BASE 0x10040000 /* Generic interrupt controller CPU interface */
#define REALVIEW_GIC1_DIST_BASE 0x10041000 /* Generic interrupt controller distributor */
#endif
......
#ifndef __ASMARM_ARCH_SCU_H
#define __ASMARM_ARCH_SCU_H
#include <asm/arch/platform.h>
#define SCU_BASE REALVIEW_MPCORE_SCU_BASE
#endif
#ifndef ASMARM_HARDWARE_ARM_SCU_H
#define ASMARM_HARDWARE_ARM_SCU_H
#include <asm/arch/scu.h>
/*
* SCU registers
*/
......
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