- 17 Dec, 2009 40 commits
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Thomas Gleixner authored
The typename member of struct irq_chip was kept for migration purposes and is obsolete since more than 2 years. Fix up the leftovers. Signed-off-by:
Thomas Gleixner <tglx@linutronix.de> Cc: linux-mips@linux-mips.org To: LKML <linux-kernel@vger.kernel.org> Cc: Ingo Molnar <mingo@elte.hu> Patchwork: http://patchwork.linux-mips.org/patch/661/Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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Wu Zhangjin authored
Loongson 2F supports CPU clock scaling. When put it into wait mode by setting the frequency as ZERO it will stay in this mode until an external interrupt wakes the CPU again. To enable clock scaling support, an external timer of a known stable rate is required. Signed-off-by:
Wu Zhangjin <wuzhangjin@gmail.com> Cc: linux-mips@linux-mips.org Cc: cpufreq@vger.kernel.org, Cc: Dave Jones <davej@redhat.com>, Cc: Dominik Brodowski <linux@dominikbrodowski.net>, Cc: yanh@lemote.com Cc: huhb@lemote.com, Patchwork: http://patchwork.linux-mips.org/patch/660/ Patchwork: http://patchwork.linux-mips.org/patch/751/Signed-off-by:
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Wu Zhangjin authored
This patch adds basic options for MIPS CPUFreq support. Since the cp0 timer's frequency is based on the processor clockrate it can not be used with CPUFReq; an additional external timer is required. Signed-off-by:
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Wu Zhangjin authored
CPUFreq support for Loongson 2F requires an external timer. Because the frequency of the MIPS Timer is related to the CPU frequency which itself is variable another timer of constant frequency is required. Export the mfgpt0 counter disable / enable operations for the coming suspend support to suspend / resume the timer. Signed-off-by:
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Wu Zhangjin authored
Add a new machtype and kernel options for the Lynloong. Signed-off-by:
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Wu Zhangjin authored
Kernel support for this machine is almost the same as Fuloong 2F; the only difference is that it uses the serial port provided by Loongson 2F processor as Yeeloong 2F does. Signed-off-by:
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David VomLehn authored
Add the Cisco Powertv cable settop box to the MIPS tree. This platform is based on a MIPS 24Kc processor with various devices integrated on the same ASIC. There are multiple models of this box, with differing configuration but the same kernel runs across the product line. Signed-off-by:
David VomLehn <dvomlehn@cisco.com> Cc: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/132/Signed-off-by:
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Akinobu Mita authored
Signed-off-by:
Akinobu Mita <akinobu.mita@gmail.com> Cc: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/637/Signed-off-by:
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Wu Zhangjin authored
Lemote Loongson 2F family machines need an external interrupt to wake the system from the suspend mode. For YeeLoong 2F and Mengloong 2F setup the keyboard interrupt as the wakeup interrupt. The new Fuloong 2F and LingLoong 2F have a button to directly send an interrupt to the CPU so there is no need to setup an interrupt. Signed-off-by:
Pavel Machek <pavel@ucw.cz> Signed-off-by:
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Wu Zhangjin authored
This patch add basic suspend support for loongson2f family machines, loongson2f have a specific feature: when we set it's frequency to ZERO, it will go into a wait mode, and then can be waked up by the external interrupt. so, if we setup suitable interrupts before putting it into wait mode, we will be able wake it up whenever we want via sending the relative interrupts to it. These interrupts are board-specific, Yeeloong2F use the keyboard interrupt and SCI interrupt, but LingLoong and Fuloong2F use the interrupts connected to the processors directly. and BTW: some old LingLoong and FuLoong2F have no such interrupts connected, so, there is no way to wake them up from suspend mode. and therefore, please do not enable the kernel support for them. The board-specific support will be added in the coming patches. Signed-off-by:
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Wu Zhangjin authored
Loongson2f support video acceleration. Signed-off-by:
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Wu Zhangjin authored
This patch adds two new kernel options: CPU_SUPPORTS_CPUFREQ and CPU_SUPPORTS_ADDRWINCFG to describe the new features of Loongons 2F and replaces the several ugly #if clauses by them. These two options will be utilized by the future loongson revisions and related drivers such as the coming Loongson 2F CPUFreq driver. Signed-off-by:
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Wu Zhangjin authored
Add default config file for Lemote Loongson 2F family machines. The resulting kernel image can be shared between Fuloong 2F, Yeeloong 2F and other Lemote Loongson 2F family machines. If you are using an old PMON, and not using a 2f box, please add a new command line argument in the boot.cfg. For example, add this argument for 8.9inches notebook: machtype=lemote-yeeloong-2f-8.9inches or machtype=8.9 More information from arch/mips/loongson/common/machtype.c. Signed-off-by: -
Wu Zhangjin authored
Fuloong 2F, Yeeloong 2F and Menglong 2F have different reset / shutdown logic. Signed-off-by:
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Wu Zhangjin authored
The generic i8259_irq() will make kernel hang on booting, so Loongson 2F needs its own polling method. IP6 is shared by the bonito interrupt and perfcounter interrupts. Signed-off-by:
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Wu Zhangjin authored
PCI support for the Fuloong 2E and Lemote Loongson 2F family machines is mostly identical with the exception of CS5536 support. Rename ops-fuloong2e.c to ops-loongson2.c then add the CS5536 support to share most of the source code among Loongson machines. Signed-off-by:
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Wu Zhangjin authored
Lemote Loongson 2F family machines use CS5536 as their south bridge and need these lowlevel interfaces to access the devices on CS5536. Virtualize the legacy devices on CS5536 as PCI devices. This way users can access the CS5536 PCI config space directly as a normal multi-function PCI 2.2 device. Signed-off-by:
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Wu Zhangjin authored
Currently rtclib is not available on Loongson family machines but the legacy RTC driver works well on them. Deselect RTC_LIB to allow the legacy RTC driver to be selected. The rtclib patch series http://www.linux-mips.org/cgi-bin/mesg.cgi?a=linux-mips&i=a91e34bf2595157830d599cb66becd52247b1819.1257383766.git.wuzhangjin%40gmail.com or, in patchworks: http://patchwork.linux-mips.org/patch/570/ http://patchwork.linux-mips.org/patch/571/ http://patchwork.linux-mips.org/patch/572/ is eventually going to switch Lemote platforms to rtclib. Signed-off-by:
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Wu Zhangjin authored
Add a new kernel option for Lemote Loongson 2F family machines. Lemote loongson2f family machines utilize the 2f revision of loongson processor and the AMD CS5536 south bridge. Family members include Fuloong 2F mini PC, Yeeloong 2F notebook, LingLoong all-in-one PC and others. Signed-off-by:
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Wu Zhangjin authored
Loongson 2F has built-in DDR2 and PCI-X controller. The PCI-X controller has a programming interface similiar to the the FPGA northbridge used on Loongson 2E. The main differences between Loongson 2E and Loongson 2F include: 1. Loongson 2F has an extra address window configuration module, which is used to map CPU address space to DDR or PCI address space, or map the PCI-DMA address space to DDR or LIO address space. 2. Loongson 2F supports 8 levels of software configurable CPu frequency which can be configured in the LOONGSON_CHIPCFG0 register. The coming cpufreq and standby support are based on this feature. Loongson.h abstracts the modules and corresponding methods are abstracted. Add other Loongson-2F-specific source code including gcc 4.4 support, PCI memory space, PCI IO space, DMA address. Signed-off-by:
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Wu Zhangjin authored
In Loongson2f IP6 is shared by bonito and perfcounters so we need to avoid do_IRQ for perfcounter when the interrupt is from bonito. Signed-off-by:
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Wu Zhangjin authored
To share the same kernel image amon different machines we have added the machtype command line support. In the old serial port implementation the UART base address is hardcoded as a macro in machine.h which breaks with machtype, so change that to discover the address dynamically. Also move the initialization of the UART base address to uart_base.c to avoid remapping twice for early_printk.c and serial.c. Signed-off-by:
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Wu Zhangjin authored
To choose code for different machines by the value of machtype it needs to be initialized as early as possible. So move initialization of mips_machtype to prom_init(). Signed-off-by:
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David Daney authored
On SMP systems, the collection of statistics can cause cache line bouncing in the lines associated with the counters. Also there are races incrementing the counters on multiple CPUs. To fix both problems, we collect the statistics in per-CPU variables, and add them up in the debugfs read operation. As a test I ran the LTP float_bessel test on a 12 CPU Octeon system. Without CONFIG_DEBUG_FS : 2602 seconds. With CONFIG_DEBUG_FS: 2640 seconds. With non-cpu-local atomic statistics: 14569 seconds. Signed-off-by:
David Daney <ddaney@caviumnetworks.com> Cc: linux-mips@linux-mips.org Signed-off-by:
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Ralf Baechle authored
Addinitrd has been superseded by initramfs ages ago. Signed-off-by: -
Wu Zhangjin authored
Enable hibernation support by default. Also enable sparsemem to avoid the hibernation failures with flatmem and save memory wasted by flatmem. Signed-off-by:
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Wu Zhangjin authored
The built-in Loongson 2E/2F northbridge in is bonito64-compatible but not identical with it. To avoid influencing the original bonito64 support and make the loongson support more maintainable, it's better to separate the Bonito64 code from the Loongson code. This also prepares the kernel for the coming Loongson 2f machines family support. Signed-off-by:
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Wu Zhangjin authored
This patch add serial port support for all of the existing loongson family machines. most of the board specific part are put in serial.c, and the base address of the serial ports are defined as macros in machine.h for sharing it between serial.c and early_printk.c Signed-off-by:
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Wu Zhangjin authored
The uart_base variable here is not a physical address, so, we replace it by unsigned char *. Signed-off-by:
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Wu Zhangjin authored
Changes indention from whitespace to tabs in arch/mips/loongson/Kconfig. Signed-off-by:
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Wu Zhangjin authored
Register reserved pages for Loongson family machines. Signed-off-by:
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Dmitri Vorobiev authored
The function prom_init_cmdline() doesn't do anything, and nobody calls the prom_getcmdline() function. Since these two are the only functions in the file arch/mips/mipssim/sim_cmdline.c, the whole file can be removed now along with the call to the no-op prom_init_cmdline() routine. Signed-off-by:
Dmitri Vorobiev <dmitri.vorobiev@movial.com> Patchwork: http://patchwork.linux-mips.org/patch/465/Signed-off-by:
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David Daney authored
Processors that support the mips64r2 ISA can in four instructions convert a shifted PGD pointer stored in the upper bits of c0_context into a usable pointer. By doing this we save a memory load and associated potential cache miss in the TLB exception handlers. Since the upper bits of c0_context were holding the CPU number, we move this to the upper bits of c0_xcontext which doesn't have enough bits to hold the PGD pointer, but has plenty for the CPU number. Signed-off-by:
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David Daney authored
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David Daney authored
The octeon-ethernet driver shares an mdio bus with the octeon-mgmt driver. Here we convert the octeon-ethernet driver to use the PHY Abstraction Layer. Signed-off-by:
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David Daney authored
The Octeon MGMT Ethernet ports are present in some members of the Octeon SOC family (cn52XX and cn56XX have them). The mdio bus connected to the MGMT PHYs is shared with the main octeon-ethernet driver, we force it to be loaded first by calling octeon_mdiobus_force_mod_depencency. The platform devices for the MGMT Ethernet ports are added in arch/mips/cavium-octeon/octeon-platform.c, and the register definitions for the ports live in arch/mips/include/asm/octeon/ along with their ilk. Although it currently is the only driver in drivers/net/octeon, the directory was created looking forward to the day that octeon-ethernet will move there from its current home in drivers/staging. Signed-off-by:
David S. Miller <davem@davemloft.net> Signed-off-by:
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David Daney authored
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David Daney authored
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David Daney authored
The Octeon SOC has two types of Ethernet ports, each type with its own driver. However, the PHYs for all the ports are controlled by a common MDIO bus. Because the mdio driver is not associated with a particular driver, but is instead a system level resource, we create s stand-alone driver for it. As for the driver, we put the register definitions in arch/mips/include/asm/octeon where most of the other Octeon register definitions live. This is a platform driver with the platform device for "mdio-octeon" being registered in the platform startup code. Signed-off-by:
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David Daney authored
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