This patch redefines the IO_ADDRESS macro in
include/asm-arm/hardware.h.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

These were mainly caused by kernel updates without testing the
MMU-less case.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

There is no MMU context switching on MMU-less systems.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

There shouldn't be any references to paging or TLBs in the MMU-less
case.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

The current arch/arm/boot/compressed/head.S code only supports cores
to ARMv6 with the old CPU Id format. This patch adds support for the
new ARMv6 with the new CPU Id and ARMv7 cores that no longer have the
ARMv4 cache operations.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

The attached patch implements Thumb-2 application support in Linux. There
are two main changes:

- Use IFAR when handling prefetch aborts
- Handle undefined instruction traps from coprocessor instructions in Thumb
  mode
Signed-off-by: Paul Brook <paul@codesourcery.com>

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

This patch enables the use of the Neon extension on ARMv7 (Cortex-A8).
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

This patch adds the support for VFPv3 (the kernel currently supports
VFPv2). The main differences are 32 double registers (compared to 16)
and missing FPINST and FPINST2 registers.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

We were previously using the ARMv6 operations but duplicated some of
the code because of the introduction of the new CPU barrier
instructions in ARMv7.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

This patch adds the necessary lines to the Makefile and Kconfig files for
enabling the compilation of the ARMv7 CPU support.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

ARMv7 can have VIPT, PIPT or ASID-tagged VIVT I-cache. This patch adds
the necessary invalidation of the I-cache when the ASID numbers are
re-used.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

This patch renames the old __cacheid_* macros to __cacheid_*_prev7 and adds
support for the new format.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

Starting with ARMv7, there are dedicated instruction for the ISB, DSB
and DMB barriers and there is no need to execute them as CP15
operations.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

This patch adds the Linux support for the ARMv7 cores.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

ARMv7 support code requires a valid stack for saving/restoring
registers as the whole D-cache flushing function is more complex. This
patch ensures that the SP register is not corrupted.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

Because of possible unpredictable behaviour caused by the overlapping
of sections and supersections during the initial memory setup (may
lead to two TLB entries for the same virtual address), this patch
disables the use of supersections for addresses < 4GB.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

This patch enables the L220 on the RealView/EB MPCore platform.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

This patch adds the support for the L210/L220 (outer) cache
controller. The cache range operations are done by index/way since L2
cache controller only accepts physical addresses.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

Other platforms other than SMP may have an outer cache.  For these, we
also need to mark the page table walks outer cacheable.  Since marking
the walks always outer cacheable apparantly has no side effects, we
might as well always mark them so.

However, we continue to only mark PTWs shared if we have SMP enabled.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

The outer cache can be L2 as on RealView/EB MPCore platform or even L3
or further on ARMv7 cores. This patch adds the generic support for
flushing the outer cache in the DMA operations.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

Currently, the mb() is defined as a DMB operation on ARMv6, even for
UP systems. This patch defines mb() as a compiler barrier only. For
the SMP case, the smp_* variants should be used anyway and the patch
defines them as DMB.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

According to ARM ARM, changes to the CP15 registers are only
guaranteed to be visible after an Instruction Synchronization Barrier
(ISB). This patch adds the ISB at the end of set_cr and
set_copro_access functions and also moves them further down in the
file, below the isb macro definition.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

Starting with ARMv6, accesses to strongly ordered memory are not
guaranteed to complete before a subsequent instruction modifying the
interrupt mask in CPSR. This can cause potential problems with masking
or acknowledging an IRQ at the device or interrupt controller level
followed by a local_irq_enable or local_irq_restore (see B2.4.3 in ARM
ARM revI). This patch adds a DSB after masking the interrupts at the
interrupt controller level to ensure that the strongly ordered memory
access was completed.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

The architecture specification states that TLB operations are
guaranteed to be complete only after the execution of a DSB (Data
Synchronisation Barrier, former Data Write Barrier or Drain Write
Buffer).
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

The ARM Architecture Reference Manual specifies that a prefetch flush
is needed after changing the DACR register (chapter B2.7.6).
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

On newer architectures (ARMv6, ARMv7), the depth of the prefetch and
branch prediction is implementation defined and there is a small risk
of wrong ASID tagging when changing TTBR0 before setting the new
context id. The recommended solution is to set a reserved ASID during
TTBR changing. This patch reserves ASID 0.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

There are three barriers - ISB, DMB and DSB for different
scenarious. This patch adds their definitions in the system.h file.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

The current lazy saving of the VFP registers is no longer possible
with thread migration on SMP. This patch implements a per-CPU
vfp-state pointer and the saving of the VFP registers at every context
switch. The registers restoring is still performed in a lazy way.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

Otherwise, the caches can become uncoherent between cores.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

RealView/EB MPCore revB and revC contains r0p0 silicon, which needs
this workaround.
Signed-off-by: Harry Fearnhamm <Harry.Fearnhamm@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

Device driver for the SMSC LAN911x/LAN921x families embedded Ethernet
chips.
Signed-off-by: Steve Glendinning <steve.glendinning@smsc.com>
Signed-off-by: Bahadir Balban <bahadir.balban@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

RealView/EB revD platform comes with the SMSC LAN9118 Ethernet
chip. This patch allows either the smc91x or the smc911x drivers to be
used with the RealView/EB platform.
Signed-off-by: Bahadir Balban <bahadir.balban@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

In some situations, the pen_release store in platform_secondary_init()
may stay forever in the write buffer while the CPU is waiting on the
boot_lock to be released in boot_secondary(). The primary CPU could
never see the pen_release update without the barriers.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

The kernel originally supported revB only. This patch enables revC by
default and adds a config option for building the kernel for the revB
platform.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

This patch adds the registration of the secondary GIC on the
baseboard, together with the IRQ chaining setup.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

The current implementation only assumes one GIC to be present in the
system. However, there are platforms with more than one cascaded interrupt
controllers (RealView/EB MPCore for example).
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

Errata 411920 - Invalidation of the Instruction Cache operation can
fail. This Errata is present in 1136, 1156 and 1176. It does not
affect the MPCore. This patch implements the ARM Ltd recommended
workaround.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>