Commit e9b7cce8 authored by David Brownell's avatar David Brownell Committed by Tony Lindgren

musb_hdrc: cleanup, mostly related to CPPI

 - Remove #ifdefs in favor of new is_cppi_enabled() macro.
 - Trim some tx-start logic, inlining it and removing MGC_{Read,Write}Csr16()
 - Remove remnant of bogus/non-existent host-side ISO bitfield.

For upstream merging, more such #ifdeffery still needs to be removed.
Signed-off-by: default avatarDavid Brownell <dbrownell@users.sourceforge.net>
parent 5261debe
......@@ -266,11 +266,10 @@ static irqreturn_t davinci_interrupt(int irq, void *__hci, struct pt_regs *r)
* resolve some of the races observed in this dispatch code??
*/
#ifdef CONFIG_USB_TI_CPPI_DMA
/* CPPI interrupts share the same IRQ line, but have their own
* mask, state, "vector", and EOI registers.
*/
{
if (is_cppi_enabled()) {
u32 cppi_tx = musb_readl(tibase, DAVINCI_TXCPPI_MASKED_REG);
u32 cppi_rx = musb_readl(tibase, DAVINCI_RXCPPI_MASKED_REG);
......@@ -280,7 +279,6 @@ static irqreturn_t davinci_interrupt(int irq, void *__hci, struct pt_regs *r)
retval = IRQ_HANDLED;
}
}
#endif
/* ack and handle non-CPPI interrupts */
tmp = musb_readl(tibase, DAVINCI_USB_INT_SRC_MASKED_REG);
......
......@@ -67,10 +67,10 @@ struct musb_hw_ep;
#define is_dma_capable() (0)
#endif
#if defined(CONFIG_USB_TI_CPPI_DMA) && defined(CONFIG_USB_MUSB_HDRC_HCD)
extern void cppi_hostdma_start(struct musb * pThis, u8 bEnd);
#ifdef CONFIG_USB_TI_CPPI_DMA
#define is_cppi_enabled() 1
#else
static inline void cppi_hostdma_start(struct musb * pThis, u8 bEnd) {}
#define is_cppi_enabled() 0
#endif
......
......@@ -566,8 +566,7 @@ static void rxstate(struct musb *pThis, struct musb_request *req)
wCsrVal = MGC_ReadCsr16(pBase, MGC_O_HDRC_RXCSR, bEnd);
#ifdef CONFIG_USB_TI_CPPI_DMA
if (is_dma_capable() && pEnd->dma) {
if (is_cppi_enabled() && pEnd->dma) {
struct dma_controller *c = pThis->pDmaController;
struct dma_channel *channel = pEnd->dma;
......@@ -593,7 +592,6 @@ static void rxstate(struct musb *pThis, struct musb_request *req)
return;
}
}
#endif
if (wCsrVal & MGC_M_RXCSR_RXPKTRDY) {
wCount = MGC_ReadCsr16(pBase, MGC_O_HDRC_RXCOUNT, bEnd);
......
......@@ -113,41 +113,32 @@ static void musb_ep_program(struct musb *pThis, u8 bEnd,
* Start transmit. Caller is responsible for locking shared resources.
* pThis must be locked.
*/
void musb_h_tx_start(struct musb *pThis, u8 bEnd)
static inline void musb_h_tx_start(struct musb_hw_ep *ep)
{
u16 wCsr;
void __iomem *pBase = pThis->pRegs;
u16 txcsr;
/* NOTE: no locks here; caller should lock */
MGC_SelectEnd(pBase, bEnd);
if (bEnd) {
wCsr = MGC_ReadCsr16(pBase, MGC_O_HDRC_TXCSR, bEnd);
wCsr |= MGC_M_TXCSR_TXPKTRDY | MGC_M_TXCSR_H_WZC_BITS;
DBG(5, "Writing TXCSR%d = %x\n", bEnd, wCsr);
MGC_WriteCsr16(pBase, MGC_O_HDRC_TXCSR, bEnd, wCsr);
/* NOTE: no locks here; caller should lock and select EP */
if (ep->bLocalEnd) {
txcsr = musb_readw(ep->regs, MGC_O_HDRC_TXCSR);
txcsr |= MGC_M_TXCSR_TXPKTRDY | MGC_M_TXCSR_H_WZC_BITS;
musb_writew(ep->regs, MGC_O_HDRC_TXCSR, txcsr);
} else {
wCsr = MGC_M_CSR0_H_SETUPPKT | MGC_M_CSR0_TXPKTRDY;
MGC_WriteCsr16(pBase, MGC_O_HDRC_CSR0, 0, wCsr);
txcsr = MGC_M_CSR0_H_SETUPPKT | MGC_M_CSR0_TXPKTRDY;
musb_writew(ep->regs, MGC_O_HDRC_CSR0, txcsr);
}
}
#ifdef CONFIG_USB_TI_CPPI_DMA
void cppi_hostdma_start(struct musb *pThis, u8 bEnd)
static inline void cppi_host_txdma_start(struct musb_hw_ep *ep)
{
void __iomem *pBase = pThis->pRegs;
u16 txCsr;
u16 txcsr;
/* NOTE: no locks here; caller should lock */
MGC_SelectEnd(pBase, bEnd);
txCsr = MGC_ReadCsr16(pBase, MGC_O_HDRC_TXCSR, bEnd);
txCsr |= MGC_M_TXCSR_DMAENAB | MGC_M_TXCSR_H_WZC_BITS;
MGC_WriteCsr16(pBase, MGC_O_HDRC_TXCSR, bEnd, txCsr);
/* NOTE: no locks here; caller should lock and select EP */
txcsr = musb_readw(ep->regs, MGC_O_HDRC_TXCSR);
txcsr |= MGC_M_TXCSR_DMAENAB | MGC_M_TXCSR_H_WZC_BITS;
musb_writew(ep->regs, MGC_O_HDRC_TXCSR, txcsr);
}
#endif
/*
* Start the URB at the front of an endpoint's queue
* end must be claimed from the caller.
......@@ -227,17 +218,10 @@ musb_start_urb(struct musb *musb, int is_in, struct musb_qh *qh)
if ((urb->transfer_flags & URB_ISO_ASAP)
|| (wFrame >= urb->start_frame)) {
/* REVISIT the SOF irq handler shouldn't duplicate
* this code... or the branch below...
* ... and we don't set urb->start_frame
* this code; and we don't init urb->start_frame...
*/
qh->frame = 0;
printk("Start --> periodic TX%s on %d\n",
pEnd->tx_channel ? " DMA" : "",
bEnd);
if (!pEnd->tx_channel)
musb_h_tx_start(musb, bEnd);
else
cppi_hostdma_start(musb, bEnd);
goto start;
} else {
qh->frame = urb->start_frame;
/* enable SOF interrupt so we can count down */
......@@ -248,13 +232,14 @@ DBG(1,"SOF for %d\n", bEnd);
}
break;
default:
start:
DBG(4, "Start TX%d %s\n", bEnd,
pEnd->tx_channel ? "dma" : "pio");
if (!pEnd->tx_channel)
musb_h_tx_start(musb, bEnd);
else
cppi_hostdma_start(musb, bEnd);
musb_h_tx_start(pEnd);
else if (is_cppi_enabled())
cppi_host_txdma_start(pEnd);
}
}
......@@ -639,17 +624,14 @@ musb_rx_reinit(struct musb *musb, struct musb_qh *qh, struct musb_hw_ep *ep)
* Program an HDRC endpoint as per the given URB
* Context: irqs blocked, controller lock held
*/
#define MGC_M_TXCSR_ISO 0 /* FIXME */
static void musb_ep_program(struct musb *pThis, u8 bEnd,
struct urb *pUrb, unsigned int is_out,
u8 * pBuffer, u32 dwLength)
{
#ifndef CONFIG_USB_INVENTRA_FIFO
struct dma_controller *pDmaController;
struct dma_channel *pDmaChannel;
u8 bDmaOk;
#endif
void __iomem *pBase = pThis->pRegs;
struct dma_controller *pDmaController;
struct dma_channel *pDmaChannel;
u8 bDmaOk;
void __iomem *pBase = pThis->pRegs;
struct musb_hw_ep *pEnd = pThis->aLocalEnd + bEnd;
struct musb_qh *qh;
u16 wPacketSize;
......@@ -671,14 +653,11 @@ static void musb_ep_program(struct musb *pThis, u8 bEnd,
MGC_SelectEnd(pBase, bEnd);
#ifndef CONFIG_USB_INVENTRA_FIFO
pDmaChannel = is_out ? pEnd->tx_channel : pEnd->rx_channel;
/* candidate for DMA? */
pDmaController = pThis->pDmaController;
/* candidate for DMA */
if (is_dma_capable() && bEnd && pDmaController) {
bDmaOk = 1;
if (bDmaOk && !pDmaChannel) {
pDmaChannel = is_out ? pEnd->tx_channel : pEnd->rx_channel;
if (!pDmaChannel) {
pDmaChannel = pDmaController->channel_alloc(
pDmaController, pEnd, is_out);
if (is_out)
......@@ -687,8 +666,7 @@ static void musb_ep_program(struct musb *pThis, u8 bEnd,
pEnd->rx_channel = pDmaChannel;
}
} else
bDmaOk = 0;
#endif /* PIO isn't the only option */
pDmaChannel = NULL;
/* make sure we clear DMAEnab, autoSet bits from previous run */
......@@ -716,7 +694,6 @@ static void musb_ep_program(struct musb *pThis, u8 bEnd,
csr &= ~(MGC_M_TXCSR_H_NAKTIMEOUT
| MGC_M_TXCSR_DMAMODE
| MGC_M_TXCSR_FRCDATATOG
| MGC_M_TXCSR_ISO
| MGC_M_TXCSR_H_RXSTALL
| MGC_M_TXCSR_H_ERROR
| MGC_M_TXCSR_FIFONOTEMPTY
......@@ -724,9 +701,7 @@ static void musb_ep_program(struct musb *pThis, u8 bEnd,
);
csr |= MGC_M_TXCSR_MODE;
if (qh->type == USB_ENDPOINT_XFER_ISOC)
csr |= MGC_M_TXCSR_ISO;
else if (usb_gettoggle(pUrb->dev,
if (usb_gettoggle(pUrb->dev,
qh->epnum, 1))
csr |= MGC_M_TXCSR_H_WR_DATATOGGLE
| MGC_M_TXCSR_H_DATATOGGLE;
......@@ -793,7 +768,7 @@ static void musb_ep_program(struct musb *pThis, u8 bEnd,
wLoadCount = min((u32) wPacketSize, dwLength);
#ifdef CONFIG_USB_INVENTRA_DMA
if (bDmaOk && pDmaChannel) {
if (pDmaChannel) {
/* clear previous state */
wCsr = MGC_ReadCsr16(pBase, MGC_O_HDRC_TXCSR, bEnd);
......@@ -836,10 +811,10 @@ static void musb_ep_program(struct musb *pThis, u8 bEnd,
pDmaChannel = pEnd->pDmaChannel = NULL;
}
}
#elif defined(CONFIG_USB_TI_CPPI_DMA)
#endif
/* candidate for DMA */
if (bDmaOk && pDmaChannel) {
if (is_cppi_enabled() && pDmaChannel) {
/* program endpoint CSRs first, then setup DMA.
* assume CPPI setup succeeds.
......@@ -878,7 +853,7 @@ static void musb_ep_program(struct musb *pThis, u8 bEnd,
*/
}
}
#endif
if (wLoadCount) {
/* ASSERT: TXCSR_DMAENAB was already cleared */
......@@ -931,7 +906,8 @@ static void musb_ep_program(struct musb *pThis, u8 bEnd,
}
/* kick things off */
#ifdef CONFIG_USB_TI_CPPI_DMA
if (is_cppi_enabled()) {
/* candidate for DMA */
if (pDmaChannel) {
pDmaChannel->dwActualLength = 0L;
......@@ -958,7 +934,8 @@ static void musb_ep_program(struct musb *pThis, u8 bEnd,
} else
csr |= MGC_M_RXCSR_DMAENAB;
}
#endif
}
csr |= MGC_M_RXCSR_H_REQPKT;
DBG(7, "RXCSR%d := %04x\n", bEnd, csr);
musb_writew(pEnd->regs, MGC_O_HDRC_RXCSR, csr);
......
......@@ -81,7 +81,6 @@ static inline struct musb_qh *first_qh(struct list_head *q)
}
extern void musb_h_tx_start(struct musb *, u8 bEnd);
extern void musb_root_disconnect(struct musb *musb);
struct usb_hcd;
......
......@@ -159,8 +159,7 @@ static int dump_ep(struct musb_ep *ep, char *buffer, unsigned max)
buf += code;
max -= code;
#ifdef CONFIG_USB_TI_CPPI_DMA
if (ep->bEndNumber) {
if (is_cppi_enabled() && ep->bEndNumber) {
unsigned cppi = ep->bEndNumber - 1;
void __iomem *base = ep->pThis->ctrl_base;
unsigned off1 = cppi << 2;
......@@ -196,7 +195,6 @@ static int dump_ep(struct musb_ep *ep, char *buffer, unsigned max)
buf += code;
max -= code;
}
#endif
if (list_empty(&ep->req_list)) {
code = snprintf(buf, max, "\t(queue empty)\n");
......@@ -294,8 +292,9 @@ dump_end_info(struct musb *pThis, u8 bEnd, char *aBuffer, unsigned max)
buf += code;
max -= code;
#ifdef CONFIG_USB_TI_CPPI_DMA
if (bEnd && pEnd->rx_channel) {
if (is_cppi_enabled()
&& bEnd
&& pEnd->rx_channel) {
unsigned cppi = bEnd - 1;
unsigned off1 = cppi << 2;
void __iomem *base;
......@@ -329,7 +328,7 @@ dump_end_info(struct musb *pThis, u8 bEnd, char *aBuffer, unsigned max)
buf += code;
max -= code;
}
#endif
if (pEnd == pThis->bulk_ep
&& !list_empty(
&pThis->in_bulk)) {
......@@ -378,8 +377,10 @@ dump_end_info(struct musb *pThis, u8 bEnd, char *aBuffer, unsigned max)
code = min(code, (int) max);
buf += code;
max -= code;
#ifdef CONFIG_USB_TI_CPPI_DMA
if (bEnd && pEnd->tx_channel) {
if (is_cppi_enabled()
&& bEnd
&& pEnd->tx_channel) {
unsigned cppi = bEnd - 1;
void __iomem *base;
void __iomem *ram;
......@@ -406,7 +407,7 @@ dump_end_info(struct musb *pThis, u8 bEnd, char *aBuffer, unsigned max)
buf += code;
max -= code;
}
#endif
if (pEnd == pThis->control_ep
&& !list_empty(
&pThis->control)) {
......@@ -563,8 +564,7 @@ static int dump_header_stats(struct musb *pThis, char *buffer)
buffer += code;
#endif /* DAVINCI */
#ifdef CONFIG_USB_TI_CPPI_DMA
if (pThis->pDmaController) {
if (is_cppi_enabled() && pThis->pDmaController) {
code = sprintf(buffer,
"CPPI: txcr=%d txsrc=%01x txena=%01x; "
"rxcr=%d rxsrc=%01x rxena=%01x "
......@@ -586,7 +586,6 @@ static int dump_header_stats(struct musb *pThis, char *buffer)
count += code;
buffer += code;
}
#endif /* CPPI */
#ifdef CONFIG_USB_GADGET_MUSB_HDRC
if (is_peripheral_enabled(pThis)) {
......
......@@ -1412,12 +1412,14 @@ void musb_dma_completion(struct musb *musb, u8 bLocalEnd, u8 bTransmit)
/* called with controller lock already held */
if (!bLocalEnd) {
#if !(defined(CONFIG_USB_TI_CPPI_DMA) || defined(CONFIG_USB_TUSB_OMAP_DMA))
/* endpoint 0 */
if (devctl & MGC_M_DEVCTL_HM)
musb_h_ep0_irq(musb);
else
musb_g_ep0_irq(musb);
#ifndef CONFIG_USB_TUSB_OMAP_DMA
if (!is_cppi_enabled()) {
/* endpoint 0 */
if (devctl & MGC_M_DEVCTL_HM)
musb_h_ep0_irq(musb);
else
musb_g_ep0_irq(musb);
}
#endif
} else {
/* endpoints 1..15 */
......
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