Commit e7211be2 authored by Catalin Marinas's avatar Catalin Marinas

ARMv7: Remove the BTAC/BTB flushing when invalidating the I-cache

I-cache invalidation in __new_context (the ASID-tagged VIVT I-cache
case) also flushes the branch target cache and therefore the explicit
BTAC/BTB flushing is not required.
Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
parent f9d21782
...@@ -51,7 +51,6 @@ void __new_context(struct mm_struct *mm) ...@@ -51,7 +51,6 @@ void __new_context(struct mm_struct *mm)
flush_tlb_all(); flush_tlb_all();
if (icache_is_vivt_asid_tagged()) { if (icache_is_vivt_asid_tagged()) {
asm("mcr p15, 0, %0, c7, c5, 0 @ invalidate I-cache\n" asm("mcr p15, 0, %0, c7, c5, 0 @ invalidate I-cache\n"
"mcr p15, 0, %0, c7, c5, 6 @ flush BTAC/BTB\n"
: :
: "r" (0)); : "r" (0));
dsb(); dsb();
......
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