Commit abe4cfb6 authored by Kevin Hilman's avatar Kevin Hilman

DaVinci: FB: fix memory addressing warnings by using physical addresses

Signed-off-by: default avatarKevin Hilman <khilman@deeprootsystems.com>
parent 276df4ad
......@@ -51,20 +51,20 @@
/*
* display controller register I/O routines
*/
static __inline__ u32 dispc_reg_in(u32 offset)
static __inline__ u32 dispc_reg_in(u32 reg)
{
return (inl(offset));
return davinci_readl(reg);
}
static __inline__ u32 dispc_reg_out(u32 offset, u32 val)
static __inline__ u32 dispc_reg_out(u32 reg, u32 val)
{
outl(val, offset);
davinci_writel(val, reg);
return (val);
}
static __inline__ u32 dispc_reg_merge(u32 offset, u32 val, u32 mask)
static __inline__ u32 dispc_reg_merge(u32 reg, u32 val, u32 mask)
{
u32 addr = offset;
u32 new_val = (inl(addr) & ~mask) | (val & mask);
outl(new_val, addr);
u32 new_val = (davinci_readl(reg) & ~mask) | (val & mask);
davinci_writel(new_val, reg);
return (new_val);
}
......
......@@ -16,9 +16,9 @@
#include <mach/io.h>
/* Base registers */
#define VPBE_REG_BASE IO_ADDRESS(0x01c72780)
#define VENC_REG_BASE IO_ADDRESS(0x01c72400)
#define OSD_REG_BASE IO_ADDRESS(0x01c72600)
#define VPBE_REG_BASE 0x01c72780
#define VENC_REG_BASE 0x01c72400
#define OSD_REG_BASE 0x01c72600
#define OSD_REG_SIZE 0x00000180
/* VPBE Global Registers */
......@@ -26,7 +26,7 @@
#define VPBE_PCR (VPBE_BASE + 0x4)
/* VPSS Clock Control Register */
#define VPSS_CLKCTL IO_ADDRESS(0x01c40044)
#define VPSS_CLKCTL 0x01c40044
/* VPBE Video Encoder / Digital LCD Subsystem Registers (VENC) */
#define VENC_VMOD (VENC_REG_BASE + 0x00)
......
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