Commit 276df4ad authored by Kevin Hilman's avatar Kevin Hilman

Merge branch 'master' of ../../omap/dev

Conflicts:
	drivers/usb/musb/davinci.c
parents 4eb10671 818862e1
No related merge requests found
......@@ -24,7 +24,7 @@ real bad - it changes the behaviour of all unaligned instructions in user
space, and might cause programs to fail unexpectedly.
To change the alignment trap behavior, simply echo a number into
/proc/sys/debug/alignment. The number is made up from various bits:
/proc/cpu/alignment. The number is made up from various bits:
bit behavior when set
--- -----------------
......
......@@ -220,14 +220,17 @@ and is between 256 and 4096 characters. It is defined in the file
Bits in debug_level correspond to a level in
ACPI_DEBUG_PRINT statements, e.g.,
ACPI_DEBUG_PRINT((ACPI_DB_INFO, ...
See Documentation/acpi/debug.txt for more information
about debug layers and levels.
The debug_level mask defaults to "info". See
Documentation/acpi/debug.txt for more information about
debug layers and levels.
Enable processor driver info messages:
acpi.debug_layer=0x20000000
Enable PCI/PCI interrupt routing info messages:
acpi.debug_layer=0x400000
Enable AML "Debug" output, i.e., stores to the Debug
object while interpreting AML:
acpi.debug_layer=0xffffffff acpi.debug_level=0x2
Enable PCI/PCI interrupt routing info messages:
acpi.debug_layer=0x400000 acpi.debug_level=0x4
Enable all messages related to ACPI hardware:
acpi.debug_layer=0x2 acpi.debug_level=0xffffffff
......
......@@ -1063,6 +1063,7 @@ Prior to version 0.9.0rc4 options had a 'snd_' prefix. This was removed.
STAC9227/9228/9229/927x
ref Reference board
ref-no-jd Reference board without HP/Mic jack detection
3stack D965 3stack
5stack D965 5stack + SPDIF
dell-3stack Dell Dimension E520
......@@ -1076,6 +1077,7 @@ Prior to version 0.9.0rc4 options had a 'snd_' prefix. This was removed.
STAC92HD73*
ref Reference board
no-jd BIOS setup but without jack-detection
dell-m6-amic Dell desktops/laptops with analog mics
dell-m6-dmic Dell desktops/laptops with digital mics
dell-m6 Dell desktops/laptops with both type of mics
......
......@@ -114,11 +114,11 @@ modules.
Then you must load the gadget serial driver. To load it as an
ACM device (recommended for interoperability), do this:
modprobe g_serial use_acm=1
modprobe g_serial
To load it as a vendor specific bulk in/out device, do this:
modprobe g_serial
modprobe g_serial use_acm=0
This will also automatically load the underlying gadget peripheral
controller driver. This must be done each time you reboot the gadget
......
......@@ -49,8 +49,10 @@ it and 002/048 sometime later.
These files can be read as binary data. The binary data consists
of first the device descriptor, then the descriptors for each
configuration of the device. That information is also shown in
text form by the /proc/bus/usb/devices file, described later.
configuration of the device. Multi-byte fields in the device and
configuration descriptors, but not other descriptors, are converted
to host endianness by the kernel. This information is also shown
in text form by the /proc/bus/usb/devices file, described later.
These files may also be used to write user-level drivers for the USB
devices. You would open the /proc/bus/usb/BBB/DDD file read/write,
......
......@@ -34,11 +34,12 @@ if usbmon is built into the kernel.
Verify that bus sockets are present.
# ls /sys/kernel/debug/usbmon
0s 0t 0u 1s 1t 1u 2s 2t 2u 3s 3t 3u 4s 4t 4u
0s 0u 1s 1t 1u 2s 2t 2u 3s 3t 3u 4s 4t 4u
#
Now you can choose to either use the sockets numbered '0' (to capture packets on
all buses), and skip to step #3, or find the bus used by your device with step #2.
Now you can choose to either use the socket '0u' (to capture packets on all
buses), and skip to step #3, or find the bus used by your device with step #2.
This allows to filter away annoying devices that talk continuously.
2. Find which bus connects to the desired device
......@@ -99,8 +100,9 @@ on the event type, but there is a set of words, common for all types.
Here is the list of words, from left to right:
- URB Tag. This is used to identify URBs is normally a kernel mode address
of the URB structure in hexadecimal.
- URB Tag. This is used to identify URBs, and is normally an in-kernel address
of the URB structure in hexadecimal, but can be a sequence number or any
other unique string, within reason.
- Timestamp in microseconds, a decimal number. The timestamp's resolution
depends on available clock, and so it can be much worse than a microsecond
......
......@@ -1527,10 +1527,10 @@ W: http://ebtables.sourceforge.net/
S: Maintained
ECRYPT FILE SYSTEM
P: Mike Halcrow, Phillip Hellewell
M: mhalcrow@us.ibm.com, phillip@hellewell.homeip.net
L: ecryptfs-devel@lists.sourceforge.net
W: http://ecryptfs.sourceforge.net/
P: Tyler Hicks, Dustin Kirkland
M: tyhicks@linux.vnet.ibm.com, kirkland@canonical.com
L: ecryptfs-devel@lists.launchpad.net
W: https://launchpad.net/ecryptfs
S: Supported
EDAC-CORE
......@@ -2191,9 +2191,9 @@ S: Supported
INOTIFY
P: John McCutchan
M: ttb@tentacle.dhs.org
M: john@johnmccutchan.com
P: Robert Love
M: rml@novell.com
M: rlove@rlove.org
L: linux-kernel@vger.kernel.org
S: Maintained
......@@ -2979,6 +2979,7 @@ MUSB MULTIPOINT HIGH SPEED DUAL-ROLE CONTROLLER
P: Felipe Balbi
M: felipe.balbi@nokia.com
L: linux-usb@vger.kernel.org
T: git gitorious.org:/musb/mainline.git
S: Maintained
MYRICOM MYRI-10G 10GbE DRIVER (MYRI10GE)
......@@ -4529,7 +4530,7 @@ S: Maintained
USB VIDEO CLASS
P: Laurent Pinchart
M: laurent.pinchart@skynet.be
L: linux-uvc-devel@lists.berlios.de
L: linux-uvc-devel@lists.berlios.de (subscribers-only)
L: video4linux-list@redhat.com
W: http://linux-uvc.berlios.de
S: Maintained
......
VERSION = 2
PATCHLEVEL = 6
SUBLEVEL = 28
EXTRAVERSION = -rc8
EXTRAVERSION =
NAME = Erotic Pickled Herring
# *DOCUMENTATION*
......
......@@ -630,7 +630,7 @@ __sa1111_probe(struct device *me, struct resource *mem, int irq)
return -ENOMEM;
sachip->clk = clk_get(me, "SA1111_CLK");
if (!sachip->clk) {
if (IS_ERR(sachip->clk)) {
ret = PTR_ERR(sachip->clk);
goto err_free;
}
......
......@@ -503,7 +503,16 @@ CONFIG_MTD_CFI_UTIL=y
# CONFIG_MTD_DOC2000 is not set
# CONFIG_MTD_DOC2001 is not set
# CONFIG_MTD_DOC2001PLUS is not set
# CONFIG_MTD_NAND is not set
CONFIG_MTD_NAND=y
# CONFIG_MTD_NAND_VERIFY_WRITE is not set
# CONFIG_MTD_NAND_ECC_SMC is not set
# CONFIG_MTD_NAND_MUSEUM_IDS is not set
CONFIG_MTD_NAND_OMAP2=y
CONFIG_MTD_NAND_IDS=y
# CONFIG_MTD_NAND_DISKONCHIP is not set
# CONFIG_MTD_NAND_NANDSIM is not set
# CONFIG_MTD_NAND_PLATFORM is not set
# CONFIG_MTD_ALAUDA is not set
CONFIG_MTD_ONENAND=y
CONFIG_MTD_ONENAND_VERIFY_WRITE=y
# CONFIG_MTD_ONENAND_GENERIC is not set
......
......@@ -115,6 +115,8 @@ EXPORT_SYMBOL(__strnlen_user);
EXPORT_SYMBOL(__strncpy_from_user);
#ifdef CONFIG_MMU
EXPORT_SYMBOL(copy_page);
EXPORT_SYMBOL(__copy_from_user);
EXPORT_SYMBOL(__copy_to_user);
EXPORT_SYMBOL(__clear_user);
......@@ -181,8 +183,6 @@ EXPORT_SYMBOL(_find_first_bit_be);
EXPORT_SYMBOL(_find_next_bit_be);
#endif
EXPORT_SYMBOL(copy_page);
#ifdef CONFIG_FUNCTION_TRACER
EXPORT_SYMBOL(mcount);
#endif
......@@ -18,6 +18,7 @@
#include <linux/personality.h>
#include <linux/kallsyms.h>
#include <linux/delay.h>
#include <linux/hardirq.h>
#include <linux/init.h>
#include <linux/uaccess.h>
......
......@@ -411,8 +411,8 @@ static void __init h2_init(void)
/* Irda */
#if defined(CONFIG_OMAP_IR) || defined(CONFIG_OMAP_IR_MODULE)
omap_writel(omap_readl(FUNC_MUX_CTRL_A) | 7, FUNC_MUX_CTRL_A);
if (!(omap_request_gpio(H2_IRDA_FIRSEL_GPIO_PIN))) {
omap_set_gpio_direction(H2_IRDA_FIRSEL_GPIO_PIN, 0);
if (!(gpio_request(H2_IRDA_FIRSEL_GPIO_PIN, "irda firsel"))) {
gpio_direction_output(H2_IRDA_FIRSEL_GPIO_PIN);
h2_irda_data.transceiver_mode = h2_transceiver_mode;
}
#endif
......
......@@ -392,9 +392,9 @@ static void __init omap_sx1_init(void)
/* turn on USB power */
/* sx1_setusbpower(1); cant do it here because i2c is not ready */
omap_request_gpio(1); /* A_IRDA_OFF */
omap_request_gpio(11); /* A_SWITCH */
omap_request_gpio(15); /* A_USB_ON */
gpio_request(1, "A_IRDA_OFF");
gpio_request(11, "A_SWITCH");
gpio_request(15, "A_USB_ON");
gpio_direction_output(1, 1); /*A_IRDA_OFF = 1 */
gpio_direction_output(11, 0); /*A_SWITCH = 0 */
gpio_direction_output(15, 0); /*A_USB_ON = 0 */
......
......@@ -22,7 +22,6 @@
#include <linux/reboot.h>
#include <linux/serial_8250.h>
#include <linux/serial_reg.h>
#include <linux/irq.h>
#include <mach/hardware.h>
#include <asm/mach-types.h>
......
......@@ -34,27 +34,50 @@ __u32 arm_idlect1_mask;
* Omap1 specific clock functions
*-------------------------------------------------------------------------*/
static void omap1_watchdog_recalc(struct clk * clk)
static void omap1_watchdog_recalc(struct clk *clk, unsigned long parent_rate,
u8 rate_storage)
{
clk->rate = clk->parent->rate / 14;
unsigned long new_rate;
new_rate = parent_rate / 14;
if (rate_storage == CURRENT_RATE)
clk->rate = new_rate;
else if (rate_storage == TEMP_RATE)
clk->temp_rate = new_rate;
}
static void omap1_uart_recalc(struct clk * clk)
static void omap1_uart_recalc(struct clk *clk, unsigned long parent_rate,
u8 rate_storage)
{
unsigned long new_rate;
unsigned int val = __raw_readl(clk->enable_reg);
if (val & clk->enable_bit)
clk->rate = 48000000;
new_rate = 48000000;
else
clk->rate = 12000000;
new_rate = 12000000;
if (rate_storage == CURRENT_RATE)
clk->rate = new_rate;
else if (rate_storage == TEMP_RATE)
clk->temp_rate = new_rate;
}
static void omap1_sossi_recalc(struct clk *clk)
static void omap1_sossi_recalc(struct clk *clk, unsigned long parent_rate,
u8 rate_storage)
{
unsigned long new_rate;
u32 div = omap_readl(MOD_CONF_CTRL_1);
div = (div >> 17) & 0x7;
div++;
clk->rate = clk->parent->rate / div;
new_rate = clk->parent->rate / div;
if (rate_storage == CURRENT_RATE)
clk->rate = new_rate;
else if (rate_storage == TEMP_RATE)
clk->temp_rate = new_rate;
}
static int omap1_clk_enable_dsp_domain(struct clk *clk)
......@@ -215,24 +238,32 @@ static int calc_dsor_exp(struct clk *clk, unsigned long rate)
return dsor_exp;
}
static void omap1_ckctl_recalc(struct clk * clk)
static void omap1_ckctl_recalc(struct clk *clk, unsigned long parent_rate,
u8 rate_storage)
{
int dsor;
unsigned long new_rate;
/* Calculate divisor encoded as 2-bit exponent */
dsor = 1 << (3 & (omap_readw(ARM_CKCTL) >> clk->rate_offset));
if (unlikely(clk->rate == clk->parent->rate / dsor))
new_rate = parent_rate / dsor;
if (unlikely(clk->rate == new_rate))
return; /* No change, quick exit */
clk->rate = clk->parent->rate / dsor;
if (unlikely(clk->flags & RATE_PROPAGATES))
propagate_rate(clk);
if (rate_storage == CURRENT_RATE)
clk->rate = new_rate;
else if (rate_storage == TEMP_RATE)
clk->temp_rate = new_rate;
}
static void omap1_ckctl_recalc_dsp_domain(struct clk * clk)
static void omap1_ckctl_recalc_dsp_domain(struct clk *clk,
unsigned long parent_rate,
u8 rate_storage)
{
int dsor;
unsigned long new_rate;
/* Calculate divisor encoded as 2-bit exponent
*
......@@ -245,12 +276,15 @@ static void omap1_ckctl_recalc_dsp_domain(struct clk * clk)
dsor = 1 << (3 & (__raw_readw(DSP_CKCTL) >> clk->rate_offset));
omap1_clk_disable(&api_ck.clk);
if (unlikely(clk->rate == clk->parent->rate / dsor))
new_rate = parent_rate / dsor;
if (unlikely(clk->rate == new_rate))
return; /* No change, quick exit */
clk->rate = clk->parent->rate / dsor;
if (unlikely(clk->flags & RATE_PROPAGATES))
propagate_rate(clk);
if (rate_storage == CURRENT_RATE)
clk->rate = new_rate;
else if (rate_storage == TEMP_RATE)
clk->temp_rate = new_rate;
}
/* MPU virtual clock functions */
......@@ -289,7 +323,7 @@ static int omap1_select_table_rate(struct clk * clk, unsigned long rate)
omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val);
ck_dpll1.rate = ptr->pll_rate;
propagate_rate(&ck_dpll1);
propagate_rate(&ck_dpll1, CURRENT_RATE);
return 0;
}
......@@ -314,9 +348,6 @@ static int omap1_clk_set_rate_dsp_domain(struct clk *clk, unsigned long rate)
ret = 0;
}
if (unlikely(ret == 0 && (clk->flags & RATE_PROPAGATES)))
propagate_rate(clk);
return ret;
}
......@@ -423,8 +454,6 @@ static int omap1_set_sossi_rate(struct clk *clk, unsigned long rate)
omap_writel(l, MOD_CONF_CTRL_1);
clk->rate = p_rate / (div + 1);
if (unlikely(clk->flags & RATE_PROPAGATES))
propagate_rate(clk);
return 0;
}
......@@ -541,9 +570,6 @@ static long omap1_clk_round_rate(struct clk *clk, unsigned long rate)
{
int dsor_exp;
if (clk->flags & RATE_FIXED)
return clk->rate;
if (clk->flags & RATE_CKCTL) {
dsor_exp = calc_dsor_exp(clk, rate);
if (dsor_exp < 0)
......@@ -583,9 +609,6 @@ static int omap1_clk_set_rate(struct clk *clk, unsigned long rate)
ret = 0;
}
if (unlikely(ret == 0 && (clk->flags & RATE_PROPAGATES)))
propagate_rate(clk);
return ret;
}
......@@ -738,7 +761,7 @@ int __init omap1_clk_init(void)
}
}
}
propagate_rate(&ck_dpll1);
propagate_rate(&ck_dpll1, CURRENT_RATE);
#else
/* Find the highest supported frequency and enable it */
if (omap1_select_table_rate(&virtual_ck_mpu, ~0)) {
......@@ -747,11 +770,11 @@ int __init omap1_clk_init(void)
omap_writew(0x2290, DPLL_CTL);
omap_writew(cpu_is_omap730() ? 0x3005 : 0x1005, ARM_CKCTL);
ck_dpll1.rate = 60000000;
propagate_rate(&ck_dpll1);
propagate_rate(&ck_dpll1, CURRENT_RATE);
}
#endif
/* Cache rates for clocks connected to ck_ref (not dpll1) */
propagate_rate(&ck_ref);
propagate_rate(&ck_ref, CURRENT_RATE);
printk(KERN_INFO "Clocking rate (xtal/DPLL1/MPU): "
"%ld.%01ld/%ld.%01ld/%ld.%01ld MHz\n",
ck_ref.rate / 1000000, (ck_ref.rate / 100000) % 10,
......
......@@ -15,16 +15,22 @@
static int omap1_clk_enable_generic(struct clk * clk);
static void omap1_clk_disable_generic(struct clk * clk);
static void omap1_ckctl_recalc(struct clk * clk);
static void omap1_watchdog_recalc(struct clk * clk);
static void omap1_ckctl_recalc(struct clk *clk, unsigned long parent_rate,
u8 rate_storage);
static void omap1_watchdog_recalc(struct clk *clk, unsigned long parent_rate,
u8 rate_storage);
static int omap1_set_sossi_rate(struct clk *clk, unsigned long rate);
static void omap1_sossi_recalc(struct clk *clk);
static void omap1_ckctl_recalc_dsp_domain(struct clk * clk);
static void omap1_sossi_recalc(struct clk *clk, unsigned long parent_rate,
u8 rate_storage);
static void omap1_ckctl_recalc_dsp_domain(struct clk *clk,
unsigned long parent_rate,
u8 rate_storage);
static int omap1_clk_enable_dsp_domain(struct clk * clk);
static int omap1_clk_set_rate_dsp_domain(struct clk * clk, unsigned long rate);
static void omap1_clk_disable_dsp_domain(struct clk * clk);
static int omap1_set_uart_rate(struct clk * clk, unsigned long rate);
static void omap1_uart_recalc(struct clk * clk);
static void omap1_uart_recalc(struct clk *clk, unsigned long parent_rate,
u8 rate_storage);
static int omap1_clk_enable_uart_functional(struct clk * clk);
static void omap1_clk_disable_uart_functional(struct clk * clk);
static int omap1_set_ext_clk_rate(struct clk * clk, unsigned long rate);
......@@ -163,7 +169,7 @@ static struct clk ck_dpll1 = {
.name = "ck_dpll1",
.parent = &ck_ref,
.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
CLOCK_IN_OMAP310 | RATE_PROPAGATES | ALWAYS_ENABLED,
CLOCK_IN_OMAP310 | ALWAYS_ENABLED,
.enable = &omap1_clk_enable_generic,
.disable = &omap1_clk_disable_generic,
};
......@@ -173,7 +179,7 @@ static struct arm_idlect1_clk ck_dpll1out = {
.name = "ck_dpll1out",
.parent = &ck_dpll1,
.flags = CLOCK_IN_OMAP16XX | CLOCK_IDLE_CONTROL |
ENABLE_REG_32BIT | RATE_PROPAGATES,
ENABLE_REG_32BIT,
.enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
.enable_bit = EN_CKOUT_ARM,
.recalc = &followparent_recalc,
......@@ -200,8 +206,7 @@ static struct clk arm_ck = {
.name = "arm_ck",
.parent = &ck_dpll1,
.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
CLOCK_IN_OMAP310 | RATE_CKCTL | RATE_PROPAGATES |
ALWAYS_ENABLED,
CLOCK_IN_OMAP310 | RATE_CKCTL | ALWAYS_ENABLED,
.rate_offset = CKCTL_ARMDIV_OFFSET,
.recalc = &omap1_ckctl_recalc,
.enable = &omap1_clk_enable_generic,
......@@ -362,7 +367,7 @@ static struct arm_idlect1_clk tc_ck = {
.parent = &ck_dpll1,
.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
CLOCK_IN_OMAP730 | CLOCK_IN_OMAP310 |
RATE_CKCTL | RATE_PROPAGATES |
RATE_CKCTL |
ALWAYS_ENABLED | CLOCK_IDLE_CONTROL,
.rate_offset = CKCTL_TCDIV_OFFSET,
.recalc = &omap1_ckctl_recalc,
......@@ -549,8 +554,8 @@ static struct uart_clk uart1_16xx = {
/* Direct from ULPD, no real parent */
.parent = &armper_ck.clk,
.rate = 48000000,
.flags = CLOCK_IN_OMAP16XX | RATE_FIXED |
ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
.flags = CLOCK_IN_OMAP16XX | ENABLE_REG_32BIT |
CLOCK_NO_IDLE_PARENT,
.enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
.enable_bit = 29,
.enable = &omap1_clk_enable_uart_functional,
......@@ -597,8 +602,8 @@ static struct uart_clk uart3_16xx = {
/* Direct from ULPD, no real parent */
.parent = &armper_ck.clk,
.rate = 48000000,
.flags = CLOCK_IN_OMAP16XX | RATE_FIXED |
ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
.flags = CLOCK_IN_OMAP16XX | ENABLE_REG_32BIT |
CLOCK_NO_IDLE_PARENT,
.enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
.enable_bit = 31,
.enable = &omap1_clk_enable_uart_functional,
......@@ -612,7 +617,7 @@ static struct clk usb_clko = { /* 6 MHz output on W4_USB_CLKO */
/* Direct from ULPD, no parent */
.rate = 6000000,
.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
CLOCK_IN_OMAP310 | RATE_FIXED | ENABLE_REG_32BIT,
CLOCK_IN_OMAP310 | ENABLE_REG_32BIT,
.enable_reg = OMAP1_IO_ADDRESS(ULPD_CLOCK_CTRL),
.enable_bit = USB_MCLK_EN_BIT,
.enable = &omap1_clk_enable_generic,
......@@ -624,7 +629,7 @@ static struct clk usb_hhc_ck1510 = {
/* Direct from ULPD, no parent */
.rate = 48000000, /* Actually 2 clocks, 12MHz and 48MHz */
.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 |
RATE_FIXED | ENABLE_REG_32BIT,
ENABLE_REG_32BIT,
.enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
.enable_bit = USB_HOST_HHC_UHOST_EN,
.enable = &omap1_clk_enable_generic,
......@@ -636,8 +641,7 @@ static struct clk usb_hhc_ck16xx = {
/* Direct from ULPD, no parent */
.rate = 48000000,
/* OTG_SYSCON_2.OTG_PADEN == 0 (not 1510-compatible) */
.flags = CLOCK_IN_OMAP16XX |
RATE_FIXED | ENABLE_REG_32BIT,
.flags = CLOCK_IN_OMAP16XX | ENABLE_REG_32BIT,
.enable_reg = OMAP1_IO_ADDRESS(OTG_BASE + 0x08), /* OTG_SYSCON_2 */
.enable_bit = 8 /* UHOST_EN */,
.enable = &omap1_clk_enable_generic,
......@@ -648,7 +652,7 @@ static struct clk usb_dc_ck = {
.name = "usb_dc_ck",
/* Direct from ULPD, no parent */
.rate = 48000000,
.flags = CLOCK_IN_OMAP16XX | RATE_FIXED,
.flags = CLOCK_IN_OMAP16XX,
.enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
.enable_bit = 4,
.enable = &omap1_clk_enable_generic,
......@@ -659,9 +663,9 @@ static struct clk mclk_1510 = {
.name = "mclk",
/* Direct from ULPD, no parent. May be enabled by ext hardware. */
.rate = 12000000,
.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | RATE_FIXED,
.enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
.enable_bit = 6,
.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310,
.enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
.enable_bit = 6,
.enable = &omap1_clk_enable_generic,
.disable = &omap1_clk_disable_generic,
};
......@@ -683,7 +687,7 @@ static struct clk bclk_1510 = {
.name = "bclk",
/* Direct from ULPD, no parent. May be enabled by ext hardware. */
.rate = 12000000,
.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | RATE_FIXED,
.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310,
.enable = &omap1_clk_enable_generic,
.disable = &omap1_clk_disable_generic,
};
......@@ -707,7 +711,7 @@ static struct clk mmc1_ck = {
.parent = &armper_ck.clk,
.rate = 48000000,
.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
CLOCK_IN_OMAP310 | RATE_FIXED | ENABLE_REG_32BIT |
CLOCK_IN_OMAP310 | ENABLE_REG_32BIT |
CLOCK_NO_IDLE_PARENT,
.enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
.enable_bit = 23,
......@@ -721,8 +725,8 @@ static struct clk mmc2_ck = {
/* Functional clock is direct from ULPD, interface clock is ARMPER */
.parent = &armper_ck.clk,
.rate = 48000000,
.flags = CLOCK_IN_OMAP16XX |
RATE_FIXED | ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
.flags = CLOCK_IN_OMAP16XX | ENABLE_REG_32BIT |
CLOCK_NO_IDLE_PARENT,
.enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
.enable_bit = 20,
.enable = &omap1_clk_enable_generic,
......@@ -732,7 +736,7 @@ static struct clk mmc2_ck = {
static struct clk virtual_ck_mpu = {
.name = "mpu",
.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
CLOCK_IN_OMAP310 | VIRTUAL_CLOCK | ALWAYS_ENABLED,
CLOCK_IN_OMAP310 | ALWAYS_ENABLED,
.parent = &arm_ck, /* Is smarter alias for */
.recalc = &followparent_recalc,
.set_rate = &omap1_select_table_rate,
......@@ -747,8 +751,7 @@ static struct clk i2c_fck = {
.name = "i2c_fck",
.id = 1,
.flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
VIRTUAL_CLOCK | CLOCK_NO_IDLE_PARENT |
ALWAYS_ENABLED,
CLOCK_NO_IDLE_PARENT | ALWAYS_ENABLED,
.parent = &armxor_ck.clk,
.recalc = &followparent_recalc,
.enable = &omap1_clk_enable_generic,
......@@ -758,8 +761,7 @@ static struct clk i2c_fck = {
static struct clk i2c_ick = {
.name = "i2c_ick",
.id = 1,
.flags = CLOCK_IN_OMAP16XX |
VIRTUAL_CLOCK | CLOCK_NO_IDLE_PARENT |
.flags = CLOCK_IN_OMAP16XX | CLOCK_NO_IDLE_PARENT |
ALWAYS_ENABLED,
.parent = &armper_ck.clk,
.recalc = &followparent_recalc,
......
......@@ -86,7 +86,7 @@ static struct resource mbox_resources[] = {
};
static struct platform_device mbox_device = {
.name = "mailbox",
.name = "omap1-mailbox",
.id = -1,
.num_resources = ARRAY_SIZE(mbox_resources),
.resource = mbox_resources,
......
/*
* Mailbox reservation modules for DSP
*
* Copyright (C) 2006 Nokia Corporation
* Copyright (C) 2006-2008 Nokia Corporation
* Written by: Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
*
* This file is subject to the terms and conditions of the GNU General Public
......@@ -17,6 +17,8 @@
#include <mach/mailbox.h>
#include <mach/irqs.h>
#define DRV_NAME "omap1-mailbox"
#define MAILBOX_ARM2DSP1 0x00
#define MAILBOX_ARM2DSP1b 0x04
#define MAILBOX_DSP2ARM1 0x08
......@@ -27,7 +29,7 @@
#define MAILBOX_DSP2ARM1_Flag 0x1c
#define MAILBOX_DSP2ARM2_Flag 0x20
unsigned long mbox_base;
static void __iomem *mbox_base;
struct omap_mbox1_fifo {
unsigned long cmd;
......@@ -40,14 +42,14 @@ struct omap_mbox1_priv {
struct omap_mbox1_fifo rx_fifo;
};
static inline int mbox_read_reg(unsigned int reg)
static inline int mbox_read_reg(size_t ofs)
{
return __raw_readw(mbox_base + reg);
return __raw_readw(mbox_base + ofs);
}
static inline void mbox_write_reg(unsigned int val, unsigned int reg)
static inline void mbox_write_reg(u32 val, size_t ofs)
{
__raw_writew(val, mbox_base + reg);
__raw_writew(val, mbox_base + ofs);
}
/* msg */
......@@ -143,7 +145,7 @@ struct omap_mbox mbox_dsp_info = {
};
EXPORT_SYMBOL(mbox_dsp_info);
static int __init omap1_mbox_probe(struct platform_device *pdev)
static int __devinit omap1_mbox_probe(struct platform_device *pdev)
{
struct resource *res;
int ret = 0;
......@@ -170,12 +172,10 @@ static int __init omap1_mbox_probe(struct platform_device *pdev)
}
mbox_dsp_info.irq = res->start;
ret = omap_mbox_register(&mbox_dsp_info);
return ret;
return omap_mbox_register(&pdev->dev, &mbox_dsp_info);
}
static int omap1_mbox_remove(struct platform_device *pdev)
static int __devexit omap1_mbox_remove(struct platform_device *pdev)
{
omap_mbox_unregister(&mbox_dsp_info);
......@@ -184,9 +184,9 @@ static int omap1_mbox_remove(struct platform_device *pdev)
static struct platform_driver omap1_mbox_driver = {
.probe = omap1_mbox_probe,
.remove = omap1_mbox_remove,
.remove = __devexit_p(omap1_mbox_remove),
.driver = {
.name = "mailbox",
.name = DRV_NAME,
},
};
......@@ -203,4 +203,7 @@ static void __exit omap1_mbox_exit(void)
module_init(omap1_mbox_init);
module_exit(omap1_mbox_exit);
MODULE_LICENSE("GPL");
MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("omap mailbox: omap1 architecture specific functions");
MODULE_AUTHOR("Hiroshi DOYU" <Hiroshi.DOYU@nokia.com>);
MODULE_ALIAS("platform:"DRV_NAME);
......@@ -132,19 +132,3 @@ config MACH_OVERO
config MACH_OMAP3_PANDORA
bool "OMAP3 Pandora"
depends on ARCH_OMAP3 && ARCH_OMAP34XX
config OMAP_TICK_GPTIMER
int "GPTIMER used for system tick timer"
depends on ARCH_OMAP2 || ARCH_OMAP3
range 1 12
default 1
help
Linux uses one of the twelve on-board OMAP GPTIMER blocks to generate
system tick interrupts. The twelve GPTIMERs have slightly
different powerdomain, source clock, and security properties
(mostly documented in the OMAP3 TRMs) that can affect the selection
of which GPTIMER to use. The historical default is GPTIMER1.
If CONFIG_OMAP_32K_TIMER is selected, Beagle may require GPTIMER12
due to hardware sensitivity to glitches on the OMAP 32kHz clock
input.
......@@ -214,7 +214,7 @@ static struct platform_device *sdp2430_devices[] __initdata = {
static void ads7846_dev_init(void)
{
if (omap_request_gpio(TS_GPIO) < 0)
if (gpio_request(TS_GPIO, "ads7846 irq") < 0)
printk(KERN_ERR "can't get ads746 pen down GPIO\n");
gpio_direction_input(TS_GPIO);
......
......@@ -195,8 +195,8 @@ static struct resource apollon_smc91x_resources[] = {
.flags = IORESOURCE_MEM,
},
[1] = {
.start = OMAP_GPIO_IRQ(APOLLON_ETHR_GPIO_IRQ),
.end = OMAP_GPIO_IRQ(APOLLON_ETHR_GPIO_IRQ),
.start = gpio_to_irq(APOLLON_ETHR_GPIO_IRQ),
.end = gpio_to_irq(APOLLON_ETHR_GPIO_IRQ),
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
},
};
......@@ -399,7 +399,7 @@ static void __init apollon_tsc_init(void)
{
/* TSC2101 */
omap_cfg_reg(N15_24XX_GPIO85);
omap_request_gpio(85);
gpio_request(85, "tsc2101 irq");
gpio_direction_input(85);
omap_cfg_reg(W14_24XX_SYS_CLKOUT); /* mclk */
......
......@@ -228,7 +228,7 @@ out:
*/
static void ads7846_dev_init(void)
{
if (omap_request_gpio(ts_gpio) < 0) {
if (gpio_request(ts_gpio, "ads7846 irq") < 0) {
printk(KERN_ERR "can't get ads746 pen down GPIO\n");
return;
}
......@@ -334,7 +334,7 @@ static inline void __init ldp_init_smc911x(void)
ldp_smc911x_resources[1].start = OMAP_GPIO_IRQ(eth_gpio);
if (omap_request_gpio(eth_gpio) < 0) {
if (gpio_request(eth_gpio, "smc911x irq") < 0) {
printk(KERN_ERR "Failed to request GPIO%d for smc911x IRQ\n",
eth_gpio);
return;
......
......@@ -27,29 +27,29 @@ static int omap3evm_onenand_setup(void __iomem *, int freq);
static struct mtd_partition omap3evm_onenand_partitions[] = {
{
.name = "xloader",
.name = "xloader-onenand",
.offset = 0,
.size = 4*(64*2048),
.mask_flags = MTD_WRITEABLE
},
{
.name = "uboot",
.name = "uboot-onenand",
.offset = MTDPART_OFS_APPEND,
.size = 15*(64*2048),
.mask_flags = MTD_WRITEABLE
},
{
.name = "params",
.name = "params-onenand",
.offset = MTDPART_OFS_APPEND,
.size = 1*(64*2048),
},
{
.name = "linux",
.name = "linux-onenand",
.offset = MTDPART_OFS_APPEND,
.size = 40*(64*2048),
},
{
.name = "jffs2",
.name = "jffs2-onenand",
.offset = MTDPART_OFS_APPEND,
.size = MTDPART_SIZ_FULL,
},
......@@ -70,6 +70,60 @@ static struct platform_device omap3evm_onenand_device = {
},
};
static struct mtd_partition omap3evm_nand_partitions[] = {
/* All the partition sizes are listed in terms of NAND block size */
{
.name = "xloader-nand",
.offset = 0,
.size = 4*(128 * 1024),
.mask_flags = MTD_WRITEABLE
},
{
.name = "uboot-nand",
.offset = MTDPART_OFS_APPEND,
.size = 14*(128 * 1024),
.mask_flags = MTD_WRITEABLE
},
{
.name = "params-nand",
.offset = MTDPART_OFS_APPEND,
.size = 2*(128 * 1024)
},
{
.name = "linux-nand",
.offset = MTDPART_OFS_APPEND,
.size = 40*(128 * 1024)
},
{
.name = "jffs2-nand",
.size = MTDPART_SIZ_FULL,
.offset = MTDPART_OFS_APPEND,
},
};
static struct omap_nand_platform_data omap3evm_nand_data = {
.parts = omap3evm_nand_partitions,
.nr_parts = ARRAY_SIZE(omap3evm_nand_partitions),
.nand_setup = NULL,
.dma_channel = -1, /* disable DMA in OMAP NAND driver */
.dev_ready = NULL,
};
static struct resource omap3evm_nand_resource = {
.flags = IORESOURCE_MEM,
};
static struct platform_device omap3evm_nand_device = {
.name = "omap2-nand",
.id = 0,
.dev = {
.platform_data = &omap3evm_nand_data,
},
.num_resources = 1,
.resource = &omap3evm_nand_resource,
};
/*
* omap3evm_onenand_setup - Set the onenand sync mode
* @onenand_base: The onenand base address in GPMC memory map
......@@ -85,29 +139,48 @@ static int omap3evm_onenand_setup(void __iomem *onenand_base, int freq)
void __init omap3evm_flash_init(void)
{
u8 cs = 0;
u8 onenandcs = GPMC_CS_NUM + 1;
u8 onenandcs = GPMC_CS_NUM + 1, nandcs = GPMC_CS_NUM + 1;
u32 gpmc_base_add = OMAP34XX_GPMC_VIRT;
while (cs < GPMC_CS_NUM) {
u32 ret = 0;
ret = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
ret = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
/*
* xloader/Uboot would have programmed the oneNAND
* xloader/Uboot would have programmed the NAND/oneNAND
* base address for us This is a ugly hack. The proper
* way of doing this is to pass the setup of u-boot up
* to kernel using kernel params - something on the
* lines of machineID. Check if oneNAND is configured
* lines of machineID. Check if NAND/oneNAND is configured
*/
if ((ret & 0x3F) == (ONENAND_MAP >> 24))
onenandcs = cs;
if ((ret & 0xC00) == 0x800) {
/* Found it!! */
if (nandcs > GPMC_CS_NUM)
nandcs = cs;
} else {
ret = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
if ((ret & 0x3F) == (ONENAND_MAP >> 24))
onenandcs = cs;
}
cs++;
}
if (onenandcs > GPMC_CS_NUM) {
printk(KERN_INFO "OneNAND: Unable to find configuration "
if ((nandcs > GPMC_CS_NUM) && (onenandcs > GPMC_CS_NUM)) {
printk(KERN_INFO "NAND/OneNAND: Unable to find configuration "
" in GPMC\n ");
return;
}
if (nandcs < GPMC_CS_NUM) {
omap3evm_nand_data.cs = nandcs;
omap3evm_nand_data.gpmc_cs_baseaddr = (void *)(gpmc_base_add +
GPMC_CS0_BASE + nandcs*GPMC_CS_SIZE);
omap3evm_nand_data.gpmc_baseaddr = (void *) (gpmc_base_add);
if (platform_device_register(&omap3evm_nand_device) < 0) {
printk(KERN_ERR "Unable to register NAND device\n");
}
}
if (onenandcs < GPMC_CS_NUM) {
omap3evm_onenand_data.cs = onenandcs;
if (platform_device_register(&omap3evm_onenand_device) < 0)
......
This diff is collapsed.
......@@ -37,6 +37,7 @@
#define OMAP3XXX_EN_DPLL_LOCKED 0x7
int omap2_clk_init(void);
int omap2_clk_register(struct clk *clk);
int omap2_clk_enable(struct clk *clk);
void omap2_clk_disable(struct clk *clk);
long omap2_clk_round_rate(struct clk *clk, unsigned long rate);
......@@ -52,7 +53,8 @@ void omap2_clk_disable_unused(struct clk *clk);
#define omap2_clk_disable_unused NULL
#endif
void omap2_clksel_recalc(struct clk *clk);
void omap2_clksel_recalc(struct clk *clk, unsigned long new_parent_rate,
u8 rate_storage);
void omap2_init_clk_clkdm(struct clk *clk);
void omap2_init_clksel_parent(struct clk *clk);
u32 omap2_clksel_get_divisor(struct clk *clk);
......@@ -60,10 +62,11 @@ u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
u32 *new_div);
u32 omap2_clksel_to_divisor(struct clk *clk, u32 field_val);
u32 omap2_divisor_to_clksel(struct clk *clk, u32 div);
void omap2_fixed_divisor_recalc(struct clk *clk);
void omap2_fixed_divisor_recalc(struct clk *clk, unsigned long new_parent_rate,
u8 rate_storage);
long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate);
int omap2_clksel_set_rate(struct clk *clk, unsigned long rate);
u32 omap2_get_dpll_rate(struct clk *clk);
u32 omap2_get_dpll_rate(struct clk *clk, unsigned long parent_rate);
int omap2_wait_clock_ready(s16 prcm_mod, u16 idlest_reg, u32 cval,
const char *name);
void omap2_clk_prepare_for_reboot(void);
......
......@@ -63,6 +63,7 @@ static struct clk *sclk;
/**
* omap2xxx_clk_get_core_rate - return the CORE_CLK rate
* @clk: pointer to the combined dpll_ck + core_ck (currently "dpll_ck")
* @parent_rate: rate of the parent of the dpll_ck
*
* Returns the CORE_CLK rate. CORE_CLK can have one of three rate
* sources on OMAP2xxx: the DPLL CLKOUT rate, DPLL CLKOUTX2, or 32KHz
......@@ -70,12 +71,13 @@ static struct clk *sclk;
* struct clk *dpll_ck, which is a composite clock of dpll_ck and
* core_ck.
*/
static u32 omap2xxx_clk_get_core_rate(struct clk *clk)
static u32 omap2xxx_clk_get_core_rate(struct clk *clk,
unsigned long parent_rate)
{
long long core_clk;
u32 v;
core_clk = omap2_get_dpll_rate(clk);
core_clk = omap2_get_dpll_rate(clk, parent_rate);
v = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
v &= OMAP24XX_CORE_CLK_SRC_MASK;
......@@ -88,6 +90,30 @@ static u32 omap2xxx_clk_get_core_rate(struct clk *clk)
return core_clk;
}
static unsigned long omap2xxx_clk_find_oppset_by_mpurate(unsigned long mpu_speed,
struct prcm_config **prcm)
{
unsigned long found_speed = 0;
struct prcm_config *p;
p = *prcm;
for (p = rate_table; p->mpu_speed; p++) {
if (!(p->flags & cpu_mask))
continue;
if (p->xtal_speed != sys_ck.rate)
continue;
if (p->mpu_speed <= mpu_speed) {
found_speed = p->mpu_speed;
break;
}
}
return found_speed;
}
static int omap2_enable_osc_ck(struct clk *clk)
{
prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK, 0,
......@@ -175,11 +201,17 @@ static long omap2_dpllcore_round_rate(unsigned long target_rate)
}
static void omap2_dpllcore_recalc(struct clk *clk)
static void omap2_dpllcore_recalc(struct clk *clk, unsigned long parent_rate,
u8 rate_storage)
{
clk->rate = omap2xxx_clk_get_core_rate(clk);
unsigned long rate;
propagate_rate(clk);
rate = omap2xxx_clk_get_core_rate(clk, parent_rate);
if (rate_storage == CURRENT_RATE)
clk->rate = rate;
else if (rate_storage == TEMP_RATE)
clk->temp_rate = rate;
}
static int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate)
......@@ -188,11 +220,8 @@ static int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate)
u32 bypass = 0;
struct prcm_config tmpset;
const struct dpll_data *dd;
unsigned long flags;
int ret = -EINVAL;
local_irq_save(flags);
cur_rate = omap2xxx_clk_get_core_rate(&dpll_ck);
cur_rate = omap2xxx_clk_get_core_rate(&dpll_ck, dpll_ck.parent->rate);
mult = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
mult &= OMAP24XX_CORE_CLK_SRC_MASK;
......@@ -203,7 +232,7 @@ static int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate)
} else if (rate != cur_rate) {
valid_rate = omap2_dpllcore_round_rate(rate);
if (valid_rate != rate)
goto dpll_exit;
return -EINVAL;
if (mult == 1)
low = curr_prcm_set->dpll_speed;
......@@ -212,7 +241,7 @@ static int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate)
dd = clk->dpll_data;
if (!dd)
goto dpll_exit;
return -EINVAL;
tmpset.cm_clksel1_pll = cm_read_mod_reg(clk->prcm_mod,
dd->mult_div1_reg);
......@@ -250,12 +279,8 @@ static int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate)
omap2xxx_sdrc_init_params(omap2xxx_sdrc_dll_is_unlocked());
omap2xxx_sdrc_reprogram(done_rate, 0);
}
omap2_dpllcore_recalc(&dpll_ck);
ret = 0;
dpll_exit:
local_irq_restore(flags);
return(ret);
return 0;
}
/**
......@@ -264,9 +289,18 @@ dpll_exit:
*
* Set virt_prcm_set's rate to the mpu_speed field of the current PRCM set.
*/
static void omap2_table_mpu_recalc(struct clk *clk)
static void omap2_table_mpu_recalc(struct clk *clk, unsigned long parent_rate,
u8 rate_storage)
{
clk->rate = curr_prcm_set->mpu_speed;
struct prcm_config *prcm;
unsigned long mpurate;
mpurate = omap2xxx_clk_find_oppset_by_mpurate(parent_rate, &prcm);
if (rate_storage == CURRENT_RATE)
clk->rate = mpurate;
else if (rate_storage == TEMP_RATE)
clk->temp_rate = mpurate;
}
/*
......@@ -306,25 +340,12 @@ static int omap2_select_table_rate(struct clk *clk, unsigned long rate)
{
u32 cur_rate, done_rate, bypass = 0, tmp;
struct prcm_config *prcm;
unsigned long found_speed = 0;
unsigned long flags;
unsigned long flags, found_speed;
if (clk != &virt_prcm_set)
return -EINVAL;
for (prcm = rate_table; prcm->mpu_speed; prcm++) {
if (!(prcm->flags & cpu_mask))
continue;
if (prcm->xtal_speed != sys_ck.rate)
continue;
if (prcm->mpu_speed <= rate) {
found_speed = prcm->mpu_speed;
break;
}
}
found_speed = omap2xxx_clk_find_oppset_by_mpurate(rate, &prcm);
if (!found_speed) {
printk(KERN_INFO "Could not set MPU rate to %luMHz\n",
rate / 1000000);
......@@ -332,7 +353,7 @@ static int omap2_select_table_rate(struct clk *clk, unsigned long rate)
}
curr_prcm_set = prcm;
cur_rate = omap2xxx_clk_get_core_rate(&dpll_ck);
cur_rate = omap2xxx_clk_get_core_rate(&dpll_ck, dpll_ck.parent->rate);
if (prcm->dpll_speed == cur_rate / 2) {
omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL, 1);
......@@ -379,7 +400,6 @@ static int omap2_select_table_rate(struct clk *clk, unsigned long rate)
local_irq_restore(flags);
}
omap2_dpllcore_recalc(&dpll_ck);
return 0;
}
......@@ -424,6 +444,7 @@ void omap2_clk_init_cpufreq_table(struct cpufreq_frequency_table **table)
#endif
static struct clk_functions omap2_clk_functions = {
.clk_register = omap2_clk_register,
.clk_enable = omap2_clk_enable,
.clk_disable = omap2_clk_disable,
.clk_round_rate = omap2_clk_round_rate,
......@@ -466,16 +487,31 @@ static u32 omap2_get_sysclkdiv(void)
return div;
}
static void omap2_osc_clk_recalc(struct clk *clk)
static void omap2_osc_clk_recalc(struct clk *clk, unsigned long parent_rate,
u8 rate_storage)
{
clk->rate = omap2_get_apll_clkin() * omap2_get_sysclkdiv();
propagate_rate(clk);
unsigned long rate;
/* XXX osc_ck on 2xxx currently is parentless */
rate = omap2_get_apll_clkin() * omap2_get_sysclkdiv();
if (rate_storage == CURRENT_RATE)
clk->rate = rate;
else if (rate_storage == TEMP_RATE)
clk->temp_rate = rate;
}
static void omap2_sys_clk_recalc(struct clk *clk)
static void omap2_sys_clk_recalc(struct clk *clk, unsigned long parent_rate,
u8 rate_storage)
{
clk->rate = clk->parent->rate / omap2_get_sysclkdiv();
propagate_rate(clk);
unsigned long rate;
rate = parent_rate / omap2_get_sysclkdiv();
if (rate_storage == CURRENT_RATE)
clk->rate = rate;
else if (rate_storage == TEMP_RATE)
clk->temp_rate = rate;
}
/*
......@@ -501,7 +537,7 @@ static int __init omap2_clk_arch_init(void)
if (!mpurate)
return -EINVAL;
if (omap2_select_table_rate(&virt_prcm_set, mpurate))
if (clk_set_rate(&virt_prcm_set, mpurate))
printk(KERN_ERR "Could not find matching MPU rate\n");
recalculate_root_clocks();
......@@ -528,8 +564,8 @@ int __init omap2_clk_init(void)
clk_init(&omap2_clk_functions);
omap2_osc_clk_recalc(&osc_ck);
omap2_sys_clk_recalc(&sys_ck);
omap2_osc_clk_recalc(&osc_ck, 0, CURRENT_RATE);
omap2_sys_clk_recalc(&sys_ck, sys_ck.parent->rate, CURRENT_RATE);
for (clkp = onchip_24xx_clks;
clkp < onchip_24xx_clks + ARRAY_SIZE(onchip_24xx_clks);
......@@ -537,19 +573,17 @@ int __init omap2_clk_init(void)
if ((*clkp)->flags & CLOCK_IN_OMAP242X && cpu_is_omap2420()) {
clk_register(*clkp);
omap2_init_clk_clkdm(*clkp);
continue;
}
if ((*clkp)->flags & CLOCK_IN_OMAP243X && cpu_is_omap2430()) {
clk_register(*clkp);
omap2_init_clk_clkdm(*clkp);
continue;
}
}
/* Check the MPU rate set by bootloader */
clkrate = omap2xxx_clk_get_core_rate(&dpll_ck);
clkrate = omap2xxx_clk_get_core_rate(&dpll_ck, dpll_ck.parent->rate);
for (prcm = rate_table; prcm->mpu_speed; prcm++) {
if (!(prcm->flags & cpu_mask))
continue;
......
This diff is collapsed.
......@@ -48,14 +48,22 @@
/**
* omap3_dpll_recalc - recalculate DPLL rate
* @clk: DPLL struct clk
* @parent_rate: rate of the DPLL's parent clock
* @rate_storage: flag indicating whether current or temporary rate is changing
*
* Recalculate and propagate the DPLL rate.
*/
static void omap3_dpll_recalc(struct clk *clk)
static void omap3_dpll_recalc(struct clk *clk, unsigned long parent_rate,
u8 rate_storage)
{
clk->rate = omap2_get_dpll_rate(clk);
unsigned long rate;
propagate_rate(clk);
rate = omap2_get_dpll_rate(clk, parent_rate);
if (rate_storage == CURRENT_RATE)
clk->rate = rate;
else if (rate_storage == TEMP_RATE)
clk->temp_rate = rate;
}
/* _omap3_dpll_write_clken - write clken_bits arg to a DPLL's enable bits */
......@@ -280,9 +288,6 @@ static int omap3_noncore_dpll_enable(struct clk *clk)
else
r = _omap3_noncore_dpll_lock(clk);
if (!r)
clk->rate = omap2_get_dpll_rate(clk);
return r;
}
......@@ -394,7 +399,7 @@ static int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate)
if (!dd)
return -EINVAL;
if (rate == omap2_get_dpll_rate(clk))
if (rate == omap2_get_dpll_rate(clk, clk->parent->rate))
return 0;
if (dd->bypass_clk->rate == rate &&
......@@ -429,8 +434,6 @@ static int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate)
}
omap3_dpll_recalc(clk);
return 0;
}
......@@ -488,12 +491,8 @@ static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
WARN_ON(new_div != 1 && new_div != 2);
/* REVISIT: Add SDRC_MR changing to this code also */
local_irq_disable();
omap3_configure_core_dpll(sp->rfr_ctrl, sp->actim_ctrla,
sp->actim_ctrlb, new_div);
local_irq_enable();
omap2_clksel_recalc(clk);
return 0;
}
......@@ -584,14 +583,18 @@ static void omap3_dpll_deny_idle(struct clk *clk)
/**
* omap3_clkoutx2_recalc - recalculate DPLL X2 output virtual clock rate
* @clk: DPLL output struct clk
* @parent_rate: rate of the parent clock of @clk
* @rate_storage: flag indicating whether current or temporary rate is changing
*
* Using parent clock DPLL data, look up DPLL state. If locked, set our
* rate to the dpll_clk * 2; otherwise, just use dpll_clk.
*/
static void omap3_clkoutx2_recalc(struct clk *clk)
static void omap3_clkoutx2_recalc(struct clk *clk, unsigned long parent_rate,
u8 rate_storage)
{
const struct dpll_data *dd;
u32 v;
unsigned long rate;
struct clk *pclk;
/* Walk up the parents of clk, looking for a DPLL */
......@@ -606,15 +609,17 @@ static void omap3_clkoutx2_recalc(struct clk *clk)
WARN_ON(!dd->enable_mask);
rate = parent_rate;
v = cm_read_mod_reg(pclk->prcm_mod, dd->control_reg) & dd->enable_mask;
v >>= __ffs(dd->enable_mask);
if (v != OMAP3XXX_EN_DPLL_LOCKED)
clk->rate = clk->parent->rate;
else
clk->rate = clk->parent->rate * 2;
if (v == OMAP3XXX_EN_DPLL_LOCKED)
rate *= 2;
if (clk->flags & RATE_PROPAGATES)
propagate_rate(clk);
if (rate_storage == CURRENT_RATE)
clk->rate = rate;
else if (rate_storage == TEMP_RATE)
clk->temp_rate = rate;
}
/* Common clock code */
......@@ -626,6 +631,7 @@ static void omap3_clkoutx2_recalc(struct clk *clk)
#if defined(CONFIG_ARCH_OMAP3)
static struct clk_functions omap2_clk_functions = {
.clk_register = omap2_clk_register,
.clk_enable = omap2_clk_enable,
.clk_disable = omap2_clk_disable,
.clk_round_rate = omap2_clk_round_rate,
......@@ -665,7 +671,7 @@ static int __init omap2_clk_arch_init(void)
/* REVISIT: not yet ready for 343x */
#if 0
if (omap2_select_table_rate(&virt_prcm_set, mpurate))
if (clk_set_rate(&virt_prcm_set, mpurate))
printk(KERN_ERR "Could not find matching MPU rate\n");
#endif
......@@ -722,10 +728,8 @@ int __init omap2_clk_init(void)
for (clkp = onchip_34xx_clks;
clkp < onchip_34xx_clks + ARRAY_SIZE(onchip_34xx_clks);
clkp++) {
if ((*clkp)->flags & cpu_clkflg) {
if ((*clkp)->flags & cpu_clkflg)
clk_register(*clkp);
omap2_init_clk_clkdm(*clkp);
}
}
/* REVISIT: Not yet ready for OMAP3 */
......
This diff is collapsed.
......@@ -567,6 +567,8 @@ int omap2_clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk)
else
omap2_clkdm_wakeup(clkdm);
pwrdm_wait_transition(clkdm->pwrdm.ptr);
return 0;
}
......
......@@ -85,13 +85,14 @@ static inline void omap_init_camera(void)
}
#endif
#if defined(CONFIG_OMAP_DSP) || defined(CONFIG_OMAP_DSP_MODULE)
#define OMAP2_MBOX_BASE IO_ADDRESS(OMAP24XX_MAILBOX_BASE)
#if defined(CONFIG_OMAP_MBOX_FWK) || defined(CONFIG_OMAP_MBOX_FWK_MODULE)
static struct resource mbox_resources[] = {
#define MBOX_REG_SIZE 0x120
static struct resource omap2_mbox_resources[] = {
{
.start = OMAP2_MBOX_BASE,
.end = OMAP2_MBOX_BASE + 0x11f,
.start = OMAP24XX_MAILBOX_BASE,
.end = OMAP24XX_MAILBOX_BASE + MBOX_REG_SIZE - 1,
.flags = IORESOURCE_MEM,
},
{
......@@ -104,20 +105,39 @@ static struct resource mbox_resources[] = {
},
};
static struct resource omap3_mbox_resources[] = {
{
.start = OMAP34XX_MAILBOX_BASE,
.end = OMAP34XX_MAILBOX_BASE + MBOX_REG_SIZE - 1,
.flags = IORESOURCE_MEM,
},
{
.start = INT_24XX_MAIL_U0_MPU,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device mbox_device = {
.name = "mailbox",
.name = "omap2-mailbox",
.id = -1,
.num_resources = ARRAY_SIZE(mbox_resources),
.resource = mbox_resources,
};
static inline void omap_init_mbox(void)
{
if (cpu_is_omap2420()) {
mbox_device.num_resources = ARRAY_SIZE(omap2_mbox_resources);
mbox_device.resource = omap2_mbox_resources;
} else if (cpu_is_omap3430()) {
mbox_device.num_resources = ARRAY_SIZE(omap3_mbox_resources);
mbox_device.resource = omap3_mbox_resources;
} else {
return;
}
platform_device_register(&mbox_device);
}
#else
static inline void omap_init_mbox(void) { }
#endif
#endif /* CONFIG_OMAP_MBOX_FWK */
#if defined(CONFIG_OMAP_STI)
......
/*
* Mailbox reservation modules for OMAP2
* Mailbox reservation modules for OMAP2/3
*
* Copyright (C) 2006 Nokia Corporation
* Copyright (C) 2006-2008 Nokia Corporation
* Written by: Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
* and Paul Mundt <paul.mundt@nokia.com>
* and Paul Mundt
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
......@@ -18,40 +18,23 @@
#include <mach/mailbox.h>
#include <mach/irqs.h>
#define MAILBOX_REVISION 0x00
#define MAILBOX_SYSCONFIG 0x10
#define MAILBOX_SYSSTATUS 0x14
#define MAILBOX_MESSAGE_0 0x40
#define MAILBOX_MESSAGE_1 0x44
#define MAILBOX_MESSAGE_2 0x48
#define MAILBOX_MESSAGE_3 0x4c
#define MAILBOX_MESSAGE_4 0x50
#define MAILBOX_MESSAGE_5 0x54
#define MAILBOX_FIFOSTATUS_0 0x80
#define MAILBOX_FIFOSTATUS_1 0x84
#define MAILBOX_FIFOSTATUS_2 0x88
#define MAILBOX_FIFOSTATUS_3 0x8c
#define MAILBOX_FIFOSTATUS_4 0x90
#define MAILBOX_FIFOSTATUS_5 0x94
#define MAILBOX_MSGSTATUS_0 0xc0
#define MAILBOX_MSGSTATUS_1 0xc4
#define MAILBOX_MSGSTATUS_2 0xc8
#define MAILBOX_MSGSTATUS_3 0xcc
#define MAILBOX_MSGSTATUS_4 0xd0
#define MAILBOX_MSGSTATUS_5 0xd4
#define MAILBOX_IRQSTATUS_0 0x100
#define MAILBOX_IRQENABLE_0 0x104
#define MAILBOX_IRQSTATUS_1 0x108
#define MAILBOX_IRQENABLE_1 0x10c
#define MAILBOX_IRQSTATUS_2 0x110
#define MAILBOX_IRQENABLE_2 0x114
#define MAILBOX_IRQSTATUS_3 0x118
#define MAILBOX_IRQENABLE_3 0x11c
static unsigned long mbox_base;
#define MAILBOX_IRQ_NOTFULL(n) (1 << (2 * (n) + 1))
#define MAILBOX_IRQ_NEWMSG(n) (1 << (2 * (n)))
#define DRV_NAME "omap2-mailbox"
#define MAILBOX_REVISION 0x000
#define MAILBOX_SYSCONFIG 0x010
#define MAILBOX_SYSSTATUS 0x014
#define MAILBOX_MESSAGE(m) (0x040 + 4 * (m))
#define MAILBOX_FIFOSTATUS(m) (0x080 + 4 * (m))
#define MAILBOX_MSGSTATUS(m) (0x0c0 + 4 * (m))
#define MAILBOX_IRQSTATUS(u) (0x100 + 8 * (u))
#define MAILBOX_IRQENABLE(u) (0x108 + 8 * (u))
#define MAILBOX_IRQ_NEWMSG(u) (1 << (2 * (u)))
#define MAILBOX_IRQ_NOTFULL(u) (1 << (2 * (u) + 1))
#define MBOX_REG_SIZE 0x120
static void __iomem *mbox_base;
struct omap_mbox2_fifo {
unsigned long msg;
......@@ -66,6 +49,7 @@ struct omap_mbox2_priv {
unsigned long irqstatus;
u32 newmsg_bit;
u32 notfull_bit;
char ctx[MBOX_REG_SIZE];
};
static struct clk *mbox_ick_handle;
......@@ -73,14 +57,14 @@ static struct clk *mbox_ick_handle;
static void omap2_mbox_enable_irq(struct omap_mbox *mbox,
omap_mbox_type_t irq);
static inline unsigned int mbox_read_reg(unsigned int reg)
static inline unsigned int mbox_read_reg(size_t ofs)
{
return __raw_readl((void __iomem *)(mbox_base + reg));
return __raw_readl(mbox_base + ofs);
}
static inline void mbox_write_reg(unsigned int val, unsigned int reg)
static inline void mbox_write_reg(u32 val, size_t ofs)
{
__raw_writel(val, (void __iomem *)(mbox_base + reg));
__raw_writel(val, mbox_base + ofs);
}
/* Mailbox H/W preparations */
......@@ -95,6 +79,9 @@ static int omap2_mbox_startup(struct omap_mbox *mbox)
}
clk_enable(mbox_ick_handle);
l = mbox_read_reg(MAILBOX_REVISION);
pr_info("omap mailbox rev %d.%d\n", (l & 0xf0) >> 4, (l & 0x0f));
/* set smart-idle & autoidle */
l = mbox_read_reg(MAILBOX_SYSCONFIG);
l |= 0x00000011;
......@@ -183,6 +170,36 @@ static int omap2_mbox_is_irq(struct omap_mbox *mbox,
return (enable & status & bit);
}
static void omap2_mbox_save_ctx(struct omap_mbox *mbox)
{
int i;
struct omap_mbox2_priv *p = mbox->priv;
for (i = 0; i < MBOX_REG_SIZE; i += sizeof(u32)) {
u32 val;
val = mbox_read_reg(i);
*(u32 *)(p->ctx + i) = val;
dev_dbg(mbox->dev, "%s\t[%02d] %08x\n", __func__, i, val);
}
}
static void omap2_mbox_restore_ctx(struct omap_mbox *mbox)
{
int i;
struct omap_mbox2_priv *p = mbox->priv;
for (i = 0; i < MBOX_REG_SIZE; i += sizeof(u32)) {
u32 val;
val = *(u32 *)(p->ctx + i);
mbox_write_reg(val, i);
dev_dbg(mbox->dev, "%s\t[%02d] %08x\n", __func__, i, val);
}
}
static struct omap_mbox_ops omap2_mbox_ops = {
.type = OMAP_MBOX_TYPE2,
.startup = omap2_mbox_startup,
......@@ -195,6 +212,8 @@ static struct omap_mbox_ops omap2_mbox_ops = {
.disable_irq = omap2_mbox_disable_irq,
.ack_irq = omap2_mbox_ack_irq,
.is_irq = omap2_mbox_is_irq,
.save_ctx = omap2_mbox_save_ctx,
.restore_ctx = omap2_mbox_restore_ctx,
};
/*
......@@ -209,15 +228,15 @@ static struct omap_mbox_ops omap2_mbox_ops = {
/* DSP */
static struct omap_mbox2_priv omap2_mbox_dsp_priv = {
.tx_fifo = {
.msg = MAILBOX_MESSAGE_0,
.fifo_stat = MAILBOX_FIFOSTATUS_0,
.msg = MAILBOX_MESSAGE(0),
.fifo_stat = MAILBOX_FIFOSTATUS(0),
},
.rx_fifo = {
.msg = MAILBOX_MESSAGE_1,
.msg_stat = MAILBOX_MSGSTATUS_1,
.msg = MAILBOX_MESSAGE(1),
.msg_stat = MAILBOX_MSGSTATUS(1),
},
.irqenable = MAILBOX_IRQENABLE_0,
.irqstatus = MAILBOX_IRQSTATUS_0,
.irqenable = MAILBOX_IRQENABLE(0),
.irqstatus = MAILBOX_IRQSTATUS(0),
.notfull_bit = MAILBOX_IRQ_NOTFULL(0),
.newmsg_bit = MAILBOX_IRQ_NEWMSG(1),
};
......@@ -229,18 +248,18 @@ struct omap_mbox mbox_dsp_info = {
};
EXPORT_SYMBOL(mbox_dsp_info);
/* IVA */
#if defined(CONFIG_ARCH_OMAP2420) /* IVA */
static struct omap_mbox2_priv omap2_mbox_iva_priv = {
.tx_fifo = {
.msg = MAILBOX_MESSAGE_2,
.fifo_stat = MAILBOX_FIFOSTATUS_2,
.msg = MAILBOX_MESSAGE(2),
.fifo_stat = MAILBOX_FIFOSTATUS(2),
},
.rx_fifo = {
.msg = MAILBOX_MESSAGE_3,
.msg_stat = MAILBOX_MSGSTATUS_3,
.msg = MAILBOX_MESSAGE(3),
.msg_stat = MAILBOX_MSGSTATUS(3),
},
.irqenable = MAILBOX_IRQENABLE_3,
.irqstatus = MAILBOX_IRQSTATUS_3,
.irqenable = MAILBOX_IRQENABLE(3),
.irqstatus = MAILBOX_IRQSTATUS(3),
.notfull_bit = MAILBOX_IRQ_NOTFULL(2),
.newmsg_bit = MAILBOX_IRQ_NEWMSG(3),
};
......@@ -250,17 +269,12 @@ static struct omap_mbox mbox_iva_info = {
.ops = &omap2_mbox_ops,
.priv = &omap2_mbox_iva_priv,
};
#endif
static int __init omap2_mbox_probe(struct platform_device *pdev)
static int __devinit omap2_mbox_probe(struct platform_device *pdev)
{
struct resource *res;
int ret = 0;
if (pdev->num_resources != 3) {
dev_err(&pdev->dev, "invalid number of resources: %d\n",
pdev->num_resources);
return -ENODEV;
}
int ret;
/* MBOX base */
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
......@@ -268,42 +282,62 @@ static int __init omap2_mbox_probe(struct platform_device *pdev)
dev_err(&pdev->dev, "invalid mem resource\n");
return -ENODEV;
}
mbox_base = res->start;
mbox_base = ioremap(res->start, res->end - res->start);
if (!mbox_base)
return -ENOMEM;
/* DSP IRQ */
/* DSP or IVA2 IRQ */
res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
if (unlikely(!res)) {
dev_err(&pdev->dev, "invalid irq resource\n");
return -ENODEV;
ret = -ENODEV;
goto err_dsp;
}
mbox_dsp_info.irq = res->start;
ret = omap_mbox_register(&mbox_dsp_info);
/* IVA IRQ */
res = platform_get_resource(pdev, IORESOURCE_IRQ, 1);
if (unlikely(!res)) {
dev_err(&pdev->dev, "invalid irq resource\n");
return -ENODEV;
ret = omap_mbox_register(&pdev->dev, &mbox_dsp_info);
if (ret)
goto err_dsp;
#if defined(CONFIG_ARCH_OMAP2420) /* IVA */
if (cpu_is_omap2420()) {
/* IVA IRQ */
res = platform_get_resource(pdev, IORESOURCE_IRQ, 1);
if (unlikely(!res)) {
dev_err(&pdev->dev, "invalid irq resource\n");
ret = -ENODEV;
goto err_iva1;
}
mbox_iva_info.irq = res->start;
ret = omap_mbox_register(&pdev->dev, &mbox_iva_info);
if (ret)
goto err_iva1;
}
mbox_iva_info.irq = res->start;
ret = omap_mbox_register(&mbox_iva_info);
#endif
return 0;
err_iva1:
omap_mbox_unregister(&mbox_dsp_info);
err_dsp:
iounmap(mbox_base);
return ret;
}
static int omap2_mbox_remove(struct platform_device *pdev)
static int __devexit omap2_mbox_remove(struct platform_device *pdev)
{
#if defined(CONFIG_ARCH_OMAP2420)
omap_mbox_unregister(&mbox_iva_info);
#endif
omap_mbox_unregister(&mbox_dsp_info);
iounmap(mbox_base);
return 0;
}
static struct platform_driver omap2_mbox_driver = {
.probe = omap2_mbox_probe,
.remove = omap2_mbox_remove,
.remove = __devexit_p(omap2_mbox_remove),
.driver = {
.name = "mailbox",
.name = DRV_NAME,
},
};
......@@ -320,4 +354,7 @@ static void __exit omap2_mbox_exit(void)
module_init(omap2_mbox_init);
module_exit(omap2_mbox_exit);
MODULE_LICENSE("GPL");
MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("omap mailbox: omap2/3 architecture specific functions");
MODULE_AUTHOR("Hiroshi DOYU <Hiroshi.DOYU@nokia.com>, Paul Mundt");
MODULE_ALIAS("platform:"DRV_NAME);
......@@ -77,6 +77,7 @@ static struct mcbsp_internal_clk omap_mcbsp_clks[] = {
.clk = {
.name = "mcbsp_clk",
.id = 1,
.clkdm = { .name = "virt_opp_clkdm" },
.enable = omap_mcbsp_clk_enable,
.disable = omap_mcbsp_clk_disable,
},
......@@ -85,6 +86,7 @@ static struct mcbsp_internal_clk omap_mcbsp_clks[] = {
.clk = {
.name = "mcbsp_clk",
.id = 2,
.clkdm = { .name = "virt_opp_clkdm" },
.enable = omap_mcbsp_clk_enable,
.disable = omap_mcbsp_clk_disable,
},
......@@ -93,6 +95,7 @@ static struct mcbsp_internal_clk omap_mcbsp_clks[] = {
.clk = {
.name = "mcbsp_clk",
.id = 3,
.clkdm = { .name = "virt_opp_clkdm" },
.enable = omap_mcbsp_clk_enable,
.disable = omap_mcbsp_clk_disable,
},
......@@ -101,6 +104,7 @@ static struct mcbsp_internal_clk omap_mcbsp_clks[] = {
.clk = {
.name = "mcbsp_clk",
.id = 4,
.clkdm = { .name = "virt_opp_clkdm" },
.enable = omap_mcbsp_clk_enable,
.disable = omap_mcbsp_clk_disable,
},
......@@ -109,6 +113,7 @@ static struct mcbsp_internal_clk omap_mcbsp_clks[] = {
.clk = {
.name = "mcbsp_clk",
.id = 5,
.clkdm = { .name = "virt_opp_clkdm" },
.enable = omap_mcbsp_clk_enable,
.disable = omap_mcbsp_clk_disable,
},
......
......@@ -459,6 +459,19 @@ MUX_CFG_34XX("AH8_34XX_GPIO29", 0x5fa,
OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT)
MUX_CFG_34XX("J25_34XX_GPIO170", 0x1c6,
OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT)
MUX_CFG_34XX("AF26_34XX_GPIO0", 0x1e0,
OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_OUTPUT)
MUX_CFG_34XX("AF22_34XX_GPIO9", 0xa18,
OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_OUTPUT)
MUX_CFG_34XX("AF6_34XX_GPIO140_UP", 0x16c,
OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT_PULLUP)
MUX_CFG_34XX("AE6_34XX_GPIO141", 0x16e,
OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_OUTPUT)
MUX_CFG_34XX("AF5_34XX_GPIO142", 0x170,
OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_OUTPUT)
MUX_CFG_34XX("AE5_34XX_GPIO143", 0x172,
OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_OUTPUT)
};
#define OMAP34XX_PINS_SZ ARRAY_SIZE(omap34xx_pins)
......
......@@ -37,141 +37,6 @@
#ifdef CONFIG_PM_DEBUG
int omap2_pm_debug = 0;
static int serial_console_clock_disabled;
static int serial_console_uart;
static unsigned int serial_console_next_disable;
static struct clk *console_iclk, *console_fclk;
static void serial_console_kick(void)
{
serial_console_next_disable = omap2_read_32k_sync_counter();
/* Keep the clocks on for 4 secs */
serial_console_next_disable += 4 * 32768;
}
static void serial_wait_tx(void)
{
static const unsigned long uart_bases[3] = {
0x4806a000, 0x4806c000, 0x4806e000
};
unsigned long lsr_reg;
int looped = 0;
/* Wait for TX FIFO and THR to get empty */
lsr_reg = IO_ADDRESS(uart_bases[serial_console_uart - 1] + (5 << 2));
while ((__raw_readb(lsr_reg) & 0x60) != 0x60)
looped = 1;
if (looped)
serial_console_kick();
}
u32 omap2_read_32k_sync_counter(void)
{
return omap_readl(OMAP2_32KSYNCT_BASE + 0x0010);
}
void serial_console_fclk_mask(u32 *f1, u32 *f2)
{
switch (serial_console_uart) {
case 1:
*f1 &= ~(1 << 21);
break;
case 2:
*f1 &= ~(1 << 22);
break;
case 3:
*f2 &= ~(1 << 2);
break;
}
}
void serial_console_sleep(int enable)
{
if (console_iclk == NULL || console_fclk == NULL)
return;
if (enable) {
BUG_ON(serial_console_clock_disabled);
if (clk_get_usecount(console_fclk) == 0)
return;
if ((int) serial_console_next_disable - (int) omap2_read_32k_sync_counter() >= 0)
return;
serial_wait_tx();
clk_disable(console_iclk);
clk_disable(console_fclk);
serial_console_clock_disabled = 1;
} else {
int serial_wakeup = 0;
u32 l;
switch (serial_console_uart) {
case 1:
l = prm_read_mod_reg(CORE_MOD, PM_WKST1);
if (l & OMAP24XX_ST_UART1_MASK)
serial_wakeup = 1;
break;
case 2:
l = prm_read_mod_reg(CORE_MOD, PM_WKST1);
if (l & OMAP24XX_ST_UART2_MASK)
serial_wakeup = 1;
break;
case 3:
l = prm_read_mod_reg(CORE_MOD, OMAP24XX_PM_WKST2);
if (l & OMAP24XX_ST_UART3_MASK)
serial_wakeup = 1;
break;
}
if (serial_wakeup)
serial_console_kick();
if (!serial_console_clock_disabled)
return;
clk_enable(console_iclk);
clk_enable(console_fclk);
serial_console_clock_disabled = 0;
}
}
void pm_init_serial_console(void)
{
const struct omap_serial_console_config *conf;
char name[16];
conf = omap_get_config(OMAP_TAG_SERIAL_CONSOLE,
struct omap_serial_console_config);
if (conf == NULL)
return;
if (conf->console_uart > 3 || conf->console_uart < 1)
return;
serial_console_uart = conf->console_uart;
sprintf(name, "uart%d_fck", conf->console_uart);
console_fclk = clk_get(NULL, name);
if (IS_ERR(console_fclk))
console_fclk = NULL;
name[6] = 'i';
console_iclk = clk_get(NULL, name);
if (IS_ERR(console_fclk))
console_iclk = NULL;
if (console_fclk == NULL || console_iclk == NULL) {
serial_console_uart = 0;
return;
}
switch (serial_console_uart) {
case 1:
prm_set_mod_reg_bits(OMAP24XX_ST_UART1_MASK, CORE_MOD,
PM_WKEN1);
break;
case 2:
prm_set_mod_reg_bits(OMAP24XX_ST_UART2_MASK, CORE_MOD,
PM_WKEN1);
break;
case 3:
prm_set_mod_reg_bits(OMAP24XX_ST_UART3_MASK, CORE_MOD,
OMAP24XX_PM_WKEN2);
break;
}
}
#define DUMP_PRM_MOD_REG(mod, reg) \
regs[reg_count].name = #mod "." #reg; \
regs[reg_count++].val = prm_read_mod_reg(mod, reg)
......
......@@ -25,18 +25,10 @@ extern void omap2_allow_sleep(void);
#ifdef CONFIG_PM_DEBUG
extern u32 omap2_read_32k_sync_counter(void);
extern void omap2_pm_dump(int mode, int resume, unsigned int us);
extern void serial_console_fclk_mask(u32 *f1, u32 *f2);
extern void pm_init_serial_console(void);
extern void serial_console_sleep(int enable);
extern int omap2_pm_debug;
#else
#define omap2_read_32k_sync_counter() 0
#define serial_console_sleep(enable) do {} while (0);
#define pm_init_serial_console() do {} while (0);
#define omap2_pm_dump(mode, resume, us) do {} while (0);
#define serial_console_fclk_mask(f1, f2) do {} while (0);
#define omap2_pm_debug 0
#endif /* CONFIG_PM_DEBUG */
#endif
......@@ -30,6 +30,7 @@
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/time.h>
#include <asm/mach/time.h>
#include <asm/mach/irq.h>
......@@ -74,7 +75,11 @@ static int omap2_fclks_active(void)
f1 = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
f2 = cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
serial_console_fclk_mask(&f1, &f2);
/* Ignore UART clocks. These are handled by UART core (serial.c) */
f1 &= ~(OMAP24XX_EN_UART1 | OMAP24XX_EN_UART2);
f2 &= ~OMAP24XX_EN_UART3;
if (f1 | f2)
return 1;
return 0;
......@@ -82,7 +87,8 @@ static int omap2_fclks_active(void)
static void omap2_enter_full_retention(void)
{
u32 l, sleep_time = 0;
u32 l;
struct timespec ts_preidle, ts_postidle, ts_idle;
/* There is 1 reference hold for all children of the oscillator
* clock, the following will remove it. If no one else uses the
......@@ -112,7 +118,7 @@ static void omap2_enter_full_retention(void)
if (omap2_pm_debug) {
omap2_pm_dump(0, 0, 0);
sleep_time = omap2_read_32k_sync_counter();
getnstimeofday(&ts_preidle);
}
/* One last check for pending IRQs to avoid extra latency due
......@@ -120,22 +126,26 @@ static void omap2_enter_full_retention(void)
if (omap_irq_pending())
goto no_sleep;
serial_console_sleep(1);
omap_uart_prepare_idle(0);
omap_uart_prepare_idle(1);
omap_uart_prepare_idle(2);
/* Jump to SRAM suspend code */
omap2_sram_suspend(sdrc_read_reg(SDRC_DLLA_CTRL),
OMAP_SDRC_REGADDR(SDRC_DLLA_CTRL),
OMAP_SDRC_REGADDR(SDRC_POWER));
no_sleep:
serial_console_sleep(0);
omap_uart_resume_idle(2);
omap_uart_resume_idle(1);
omap_uart_resume_idle(0);
if (omap2_pm_debug) {
unsigned long long tmp;
u32 resume_time;
resume_time = omap2_read_32k_sync_counter();
tmp = resume_time - sleep_time;
tmp *= 1000000;
omap2_pm_dump(0, 1, tmp / 32768);
getnstimeofday(&ts_postidle);
ts_idle = timespec_sub(ts_postidle, ts_preidle);
tmp = timespec_to_ns(&ts_idle) * NSEC_PER_USEC;
omap2_pm_dump(0, 1, tmp);
}
omap2_gpio_resume_after_retention();
......@@ -196,8 +206,8 @@ static int omap2_allow_mpu_retention(void)
static void omap2_enter_mpu_retention(void)
{
u32 sleep_time = 0;
int only_idle = 0;
struct timespec ts_preidle, ts_postidle, ts_idle;
/* Putting MPU into the WFI state while a transfer is active
* seems to cause the I2C block to timeout. Why? Good question. */
......@@ -225,19 +235,18 @@ static void omap2_enter_mpu_retention(void)
if (omap2_pm_debug) {
omap2_pm_dump(only_idle ? 2 : 1, 0, 0);
sleep_time = omap2_read_32k_sync_counter();
getnstimeofday(&ts_preidle);
}
omap2_sram_idle();
if (omap2_pm_debug) {
unsigned long long tmp;
u32 resume_time;
resume_time = omap2_read_32k_sync_counter();
tmp = resume_time - sleep_time;
tmp *= 1000000;
omap2_pm_dump(only_idle ? 2 : 1, 1, tmp / 32768);
getnstimeofday(&ts_postidle);
ts_idle = timespec_sub(ts_postidle, ts_preidle);
tmp = timespec_to_ns(&ts_idle) * NSEC_PER_USEC;
omap2_pm_dump(only_idle ? 2 : 1, 1, tmp);
}
}
......@@ -249,7 +258,7 @@ static int omap2_can_sleep(void)
return 0;
if (atomic_read(&sleep_block) > 0)
return 0;
if (clk_get_usecount(osc_ck) > 1)
if (osc_ck->usecount > 1)
return 0;
if (omap_dma_running())
return 0;
......@@ -303,6 +312,7 @@ static int omap2_pm_suspend(void)
mir1 = omap_readl(0x480fe0a4);
omap_writel(1 << 5, 0x480fe0ac);
omap_uart_prepare_suspend();
omap2_enter_full_retention();
omap_writel(mir1, 0x480fe0a4);
......@@ -520,8 +530,6 @@ int __init omap2_pm_init(void)
prcm_setup_regs();
pm_init_serial_console();
/* Hack to prevent MPU retention when STI console is enabled. */
{
const struct omap_sti_console_config *sti;
......
......@@ -29,6 +29,8 @@
#include <mach/pm.h>
#include <mach/clockdomain.h>
#include <mach/powerdomain.h>
#include <mach/serial.h>
#include <mach/control.h>
#include "cm.h"
#include "cm-regbits-34xx.h"
......@@ -171,9 +173,15 @@ static void omap_sram_idle(void)
disable_smartreflex(SR2);
omap2_gpio_prepare_for_retention();
omap_uart_prepare_idle(0);
omap_uart_prepare_idle(1);
omap_uart_prepare_idle(2);
_omap_sram_idle(NULL, save_state);
omap_uart_resume_idle(2);
omap_uart_resume_idle(1);
omap_uart_resume_idle(0);
omap2_gpio_resume_after_retention();
/* Enable smartreflex after WFI */
......@@ -210,6 +218,11 @@ static int omap3_fclks_active(void)
CM_FCLKEN);
fck_per = cm_read_mod_reg(OMAP3430_PER_MOD,
CM_FCLKEN);
/* Ignore UART clocks. These are handled by UART core (serial.c) */
fck_core1 &= ~(OMAP3430_EN_UART1 | OMAP3430_EN_UART2);
fck_per &= ~OMAP3430_EN_UART3;
if (fck_core1 | fck_core3 | fck_sgx | fck_dss |
fck_cam | fck_per | fck_usbhost)
return 1;
......@@ -220,6 +233,8 @@ static int omap3_can_sleep(void)
{
if (!enable_dyn_sleep)
return 0;
if (!omap_uart_can_sleep())
return 0;
if (omap3_fclks_active())
return 0;
if (atomic_read(&sleep_block) > 0)
......@@ -312,6 +327,7 @@ static int omap3_pm_suspend(void)
goto restore;
}
omap_uart_prepare_suspend();
omap_sram_idle();
restore:
......@@ -363,8 +379,57 @@ static struct platform_suspend_ops omap_pm_ops = {
.valid = suspend_valid_only_mem,
};
/**
* omap3_iva_idle(): ensure IVA is in idle so it can be put into
* retention
*
* In cases where IVA2 is activated by bootcode, it may prevent
* full-chip retention or off-mode because it is not idle. This
* function forces the IVA2 into idle state so it can go
* into retention/off and thus allow full-chip retention/off.
*
**/
static void __init omap3_iva_idle(void)
{
/* ensure IVA2 clock is disabled */
cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
/* Reset IVA2 */
prm_write_mod_reg(OMAP3430_RST1_IVA2 |
OMAP3430_RST2_IVA2 |
OMAP3430_RST3_IVA2,
OMAP3430_IVA2_MOD, RM_RSTCTRL);
/* Enable IVA2 clock */
cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2,
OMAP3430_IVA2_MOD, CM_FCLKEN);
/* Set IVA2 boot mode to 'idle' */
omap_ctrl_writel(OMAP3_IVA2_BOOTMOD_IDLE,
OMAP343X_CONTROL_IVA2_BOOTMOD);
/* Un-reset IVA2 */
prm_write_mod_reg(0, OMAP3430_IVA2_MOD, RM_RSTCTRL);
/* Disable IVA2 clock */
cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
/* Reset IVA2 */
prm_write_mod_reg(OMAP3430_RST1_IVA2 |
OMAP3430_RST2_IVA2 |
OMAP3430_RST3_IVA2,
OMAP3430_IVA2_MOD, RM_RSTCTRL);
}
static void __init prcm_setup_regs(void)
{
/* reset modem */
prm_write_mod_reg(OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON |
OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST,
CORE_MOD, RM_RSTCTRL);
prm_write_mod_reg(0, CORE_MOD, RM_RSTCTRL);
/* XXX Reset all wkdeps. This should be done when initializing
* powerdomains */
prm_write_mod_reg(0, OMAP3430_IVA2_MOD, PM_WKDEP);
......@@ -505,15 +570,19 @@ static void __init prcm_setup_regs(void)
OMAP3_PRM_CLKSRC_CTRL_OFFSET);
/* setup wakup source */
prm_write_mod_reg(OMAP3430_EN_IO | OMAP3430_EN_GPIO1 | OMAP3430_EN_GPT1,
prm_write_mod_reg(OMAP3430_EN_IO | OMAP3430_EN_GPIO1 |
OMAP3430_EN_GPT1 | OMAP3430_EN_GPT12,
WKUP_MOD, PM_WKEN);
/* No need to write EN_IO, that is always enabled */
prm_write_mod_reg(OMAP3430_EN_GPIO1 | OMAP3430_EN_GPT1,
prm_write_mod_reg(OMAP3430_EN_GPIO1 | OMAP3430_EN_GPT1 |
OMAP3430_EN_GPT12,
WKUP_MOD, OMAP3430_PM_MPUGRPSEL);
/* For some reason IO doesn't generate wakeup event even if
* it is selected to mpu wakeup goup */
prm_write_mod_reg(OMAP3430_IO_EN | OMAP3430_WKUP_EN,
OCP_MOD, OMAP2_PRM_IRQENABLE_MPU_OFFSET);
omap3_iva_idle();
}
static int __init pwrdms_setup(struct powerdomain *pwrdm)
......
......@@ -276,6 +276,8 @@
/* CM_FCLKEN_WKUP, CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */
#define OMAP3430_EN_GPIO1 (1 << 3)
#define OMAP3430_EN_GPIO1_SHIFT 3
#define OMAP3430_EN_GPT12 (1 << 1)
#define OMAP3430_EN_GPT12_SHIFT 1
#define OMAP3430_EN_GPT1 (1 << 0)
#define OMAP3430_EN_GPT1_SHIFT 0
......
......@@ -58,7 +58,7 @@ struct omap_sdrc_params *omap2_sdrc_get_params(unsigned long r)
sp = sdrc_init_params;
while (sp->rate != r)
while (sp->rate && sp->rate != r)
sp++;
if (!sp->rate)
......
This diff is collapsed.
......@@ -93,9 +93,8 @@ ENTRY(omap24xx_cpu_suspend)
orr r4, r4, #0x40 @ enable self refresh on idle req
mov r5, #0x2000 @ set delay (DPLL relock + DLL relock)
str r4, [r2] @ make it so
mov r2, #0
nop
mcr p15, 0, r2, c7, c0, 4 @ wait for interrupt
mcr p15, 0, r3, c7, c0, 4 @ wait for interrupt
nop
loop:
subs r5, r5, #0x1 @ awake, wait just a bit
......
......@@ -53,13 +53,6 @@ struct omap_sr {
void __iomem *vpbase_addr;
};
/* Custom clocks to enable SR specific enable/disable functions. */
struct sr_custom_clk {
struct clk clk; /* meta-clock with custom enable/disable calls */
struct clk *fck; /* actual functional clock */
struct omap_sr *sr;
};
#define SR_REGADDR(offs) (sr->srbase_addr + offset)
static inline void sr_write_reg(struct omap_sr *sr, unsigned offset, u32 value)
......@@ -84,38 +77,28 @@ static inline u32 sr_read_reg(struct omap_sr *sr, unsigned offset)
return __raw_readl(SR_REGADDR(offset));
}
/* Custom clock handling functions */
static int sr_clk_enable(struct clk *clk)
static int sr_clk_enable(struct omap_sr *sr)
{
struct sr_custom_clk *sr_clk = container_of(clk, struct sr_custom_clk,
clk);
if (clk_enable(sr_clk->fck) != 0) {
printk(KERN_ERR "Could not enable %s\n", sr_clk->fck->name);
goto clk_enable_err;
if (clk_enable(sr->clk) != 0) {
printk(KERN_ERR "Could not enable %s\n", sr->clk->name);
return -1;
}
/* set fclk- active , iclk- idle */
sr_modify_reg(sr_clk->sr, ERRCONFIG, SR_CLKACTIVITY_MASK,
SR_CLKACTIVITY_IOFF_FON);
sr_modify_reg(sr, ERRCONFIG, SR_CLKACTIVITY_MASK,
SR_CLKACTIVITY_IOFF_FON);
return 0;
clk_enable_err:
return -1;
}
static void sr_clk_disable(struct clk *clk)
static void sr_clk_disable(struct omap_sr *sr)
{
struct sr_custom_clk *sr_clk = container_of(clk, struct sr_custom_clk,
clk);
/* set fclk, iclk- idle */
sr_modify_reg(sr_clk->sr, ERRCONFIG, SR_CLKACTIVITY_MASK,
SR_CLKACTIVITY_IOFF_FOFF);
sr_modify_reg(sr, ERRCONFIG, SR_CLKACTIVITY_MASK,
SR_CLKACTIVITY_IOFF_FOFF);
clk_disable(sr_clk->fck);
sr_clk->sr->is_sr_reset = 1;
clk_disable(sr->clk);
sr->is_sr_reset = 1;
}
static struct omap_sr sr1 = {
......@@ -134,24 +117,6 @@ static struct omap_sr sr2 = {
.srbase_addr = OMAP2_IO_ADDRESS(OMAP34XX_SR2_BASE),
};
static struct sr_custom_clk sr1_custom_clk = {
.clk = {
.name = "sr1_custom_clk",
.enable = sr_clk_enable,
.disable = sr_clk_disable,
},
.sr = &sr1,
};
static struct sr_custom_clk sr2_custom_clk = {
.clk = {
.name = "sr2_custom_clk",
.enable = sr_clk_enable,
.disable = sr_clk_disable,
},
.sr = &sr2,
};
static void cal_reciprocal(u32 sensor, u32 *sengain, u32 *rnsen)
{
u32 gn, rn, mul;
......@@ -181,20 +146,6 @@ static u32 cal_test_nvalue(u32 sennval, u32 senpval)
(rnsenn << NVALUERECIPROCAL_RNSENN_SHIFT));
}
static void sr_clk_init(struct sr_custom_clk *sr_clk)
{
if (sr_clk->sr->srid == SR1) {
sr_clk->fck = clk_get(NULL, "sr1_fck");
if (IS_ERR(sr_clk->fck))
printk(KERN_ERR "Could not get sr1_fck\n");
} else if (sr_clk->sr->srid == SR2) {
sr_clk->fck = clk_get(NULL, "sr2_fck");
if (IS_ERR(sr_clk->fck))
printk(KERN_ERR "Could not get sr2_fck\n");
}
clk_register(&sr_clk->clk);
}
static void sr_set_clk_length(struct omap_sr *sr)
{
struct clk *osc_sys_ck;
......@@ -511,7 +462,7 @@ void sr_start_vddautocomap(int srid, u32 target_opp_no)
sr = &sr2;
if (sr->is_sr_reset == 1) {
clk_enable(sr->clk);
sr_clk_enable(sr);
sr_configure(sr);
}
......@@ -524,7 +475,7 @@ void sr_start_vddautocomap(int srid, u32 target_opp_no)
printk(KERN_WARNING "SR%d: VDD autocomp not activated\n", srid);
sr->is_autocomp_active = 0;
if (sr->is_sr_reset == 1)
clk_disable(sr->clk);
sr_clk_disable(sr);
}
}
EXPORT_SYMBOL(sr_start_vddautocomap);
......@@ -540,7 +491,7 @@ int sr_stop_vddautocomap(int srid)
if (sr->is_autocomp_active == 1) {
sr_disable(sr);
clk_disable(sr->clk);
sr_clk_disable(sr);
sr->is_autocomp_active = 0;
return SR_TRUE;
} else {
......@@ -565,7 +516,7 @@ void enable_smartreflex(int srid)
if (sr->is_autocomp_active == 1) {
if (sr->is_sr_reset == 1) {
/* Enable SR clks */
clk_enable(sr->clk);
sr_clk_enable(sr);
if (srid == SR1)
target_opp_no = get_opp_no(current_vdd1_opp);
......@@ -575,7 +526,7 @@ void enable_smartreflex(int srid)
sr_configure(sr);
if (!sr_enable(sr, target_opp_no))
clk_disable(sr->clk);
sr_clk_disable(sr);
}
}
}
......@@ -598,7 +549,7 @@ void disable_smartreflex(int srid)
~SRCONFIG_SRENABLE);
/* Disable SR clk */
clk_disable(sr->clk);
sr_clk_disable(sr);
if (sr->srid == SR1) {
/* Disable VP1 */
prm_clear_mod_reg_bits(PRM_VP1_CONFIG_VPENABLE,
......@@ -774,10 +725,8 @@ static int __init omap3_sr_init(void)
current_vdd2_opp = PRCM_VDD1_OPP1;
}
if (cpu_is_omap34xx()) {
sr_clk_init(&sr1_custom_clk);
sr_clk_init(&sr2_custom_clk);
sr1.clk = clk_get(NULL, "sr1_custom_clk");
sr2.clk = clk_get(NULL, "sr2_custom_clk");
sr1.clk = clk_get(NULL, "sr1_fck");
sr2.clk = clk_get(NULL, "sr2_fck");
}
sr_set_clk_length(&sr1);
sr_set_clk_length(&sr2);
......
......@@ -12,9 +12,8 @@ extern void clear_reset_status(unsigned int mask);
/**
* init_gpio_reset() - register GPIO as reset generator
*
* @gpio - gpio nr
* @output - set gpio as out/low instead of input during normal work
* @gpio: gpio nr
* @output: set gpio as out/low instead of input during normal work
*/
extern int init_gpio_reset(int gpio, int output);
......
......@@ -11,6 +11,7 @@
#include <linux/module.h>
#include <linux/signal.h>
#include <linux/mm.h>
#include <linux/hardirq.h>
#include <linux/init.h>
#include <linux/kprobes.h>
#include <linux/uaccess.h>
......
......@@ -180,7 +180,7 @@ config OMAP_MBOX_FWK
default n
help
Say Y here if you want to use OMAP Mailbox framework support for
DSP and IVA1.0 in OMAP1/2.
DSP, IVA1.0 and IVA2 in OMAP1/2/3.
choice
prompt "System timer"
......@@ -214,6 +214,21 @@ config OMAP_32K_TIMER_HZ
Kernel internal timer frequency should be a divisor of 32768,
such as 64 or 128.
config OMAP_TICK_GPTIMER
int "GPTIMER used for system tick timer"
depends on ARCH_OMAP2 || ARCH_OMAP3
range 1 12
default 1
help
Linux uses one of the twelve on-board OMAP GPTIMER blocks to generate
system tick interrupts. The twelve GPTIMERs have slightly
different powerdomain, source clock, and security properties
(mostly documented in the OMAP3 TRMs) that can affect the selection
of which GPTIMER to use. The historical default is GPTIMER1.
If CONFIG_OMAP_32K_TIMER is selected, Beagle may require GPTIMER12
due to hardware sensitivity to glitches on the OMAP 32kHz clock
input.
config OMAP_DM_TIMER
bool "Use dual-mode timer"
depends on ARCH_OMAP16XX || ARCH_OMAP24XX || ARCH_OMAP34XX
......
......@@ -23,6 +23,8 @@
#include <linux/cpufreq.h>
#include <linux/debugfs.h>
#include <linux/io.h>
#include <linux/bootmem.h>
#include <linux/slab.h>
#include <mach/clock.h>
......@@ -32,6 +34,142 @@ static DEFINE_SPINLOCK(clockfw_lock);
static struct clk_functions *arch_clock;
/**
* omap_clk_for_each_child - call callback on each child clock of clk
* @clk: struct clk * to use as the "parent"
* @parent_rate: rate of the parent of @clk to pass along
* @rate_storage: flag indicating whether current or temporary rates are used
* @cb: pointer to a callback function
*
* For each child clock of @clk, call the callback function @cb, passing
* along the contents of @parent_rate and @rate_storage. If the callback
* function returns non-zero, terminate the function and pass along the
* return value.
*/
static int omap_clk_for_each_child(struct clk *clk, unsigned long parent_rate,
u8 rate_storage,
int (*cb)(struct clk *clk,
unsigned long parent_rate,
u8 rate_storage))
{
struct clk_child *child;
int ret;
list_for_each_entry(child, &clk->children, node) {
ret = (*cb)(child->clk, parent_rate, rate_storage);
if (ret)
break;
}
return ret;
}
/**
* omap_clk_has_children - does clk @clk have any child clocks?
* @clk: struct clk * to test for child clocks
*
* If clock @clk has any child clocks, return 1; otherwise, return 0.
*/
static int omap_clk_has_children(struct clk *clk)
{
return (list_empty(&clk->children)) ? 0 : 1;
}
/**
* _do_propagate_rate - callback function for rate propagation
* @clk: struct clk * to recalc and propagate from
* @parent_rate: rate of the parent of @clk, to use in recalculation
* @rate_storage: flag indicating whether current or temporary rates are used
*
* If @clk has a recalc function, call it. If @clk has any children,
* propagate @clk's rate. Returns 0.
*/
static int _do_propagate_rate(struct clk *clk, unsigned long parent_rate,
u8 rate_storage)
{
if (clk->recalc)
clk->recalc(clk, parent_rate, rate_storage);
if (omap_clk_has_children(clk))
propagate_rate(clk, rate_storage);
return 0;
}
/**
* omap_clk_add_child - add a child clock @clk2 to @clk
* @clk: parent struct clk *
* @clk2: new child struct clk *
*
* Add a child clock @clk2 to the list of children of parent clock
* @clk. Will potentially allocate memory from bootmem or, if
* available, from slab. Must only be called with the clock framework
* spinlock held. No return value.
*/
void omap_clk_add_child(struct clk *clk, struct clk *clk2)
{
struct clk_child *child;
int reuse = 0;
if (!clk->children.next)
INIT_LIST_HEAD(&clk->children);
list_for_each_entry(child, &clk->children, node) {
if (child->flags & CLK_CHILD_DELETED) {
reuse = 1;
child->flags &= ~CLK_CHILD_DELETED;
break;
}
}
if (!reuse) {
if (slab_is_available())
child = kmalloc(sizeof(struct clk_child), GFP_ATOMIC);
else
child = alloc_bootmem(sizeof(struct clk_child));
if (!child) {
WARN_ON(1);
return;
}
memset(child, 0, sizeof(struct clk_child));
if (slab_is_available())
child->flags |= CLK_CHILD_SLAB_ALLOC;
}
child->clk = clk2;
list_add_tail(&child->node, &clk->children);
}
/**
* omap_clk_del_child - add a child clock @clk2 to @clk
* @clk: parent struct clk *
* @clk2: former child struct clk *
*
* Remove a child clock @clk2 from the list of children of parent
* clock @clk. Must only be called with the clock framework spinlock
* held. No return value.
*/
void omap_clk_del_child(struct clk *clk, struct clk *clk2)
{
struct clk_child *child, *tmp;
/* Loop over all existing clk_childs, when found, deallocate */
list_for_each_entry_safe(child, tmp, &clk->children, node) {
if (child->clk == clk2) {
list_del(&child->node);
if (child->flags & CLK_CHILD_SLAB_ALLOC) {
kfree(child);
} else {
child->clk = NULL;
child->flags |= CLK_CHILD_DELETED;
}
break;
}
}
}
/*-------------------------------------------------------------------------
* Standard clock functions defined in include/linux/clk.h
*-------------------------------------------------------------------------*/
......@@ -53,15 +191,14 @@ struct clk * clk_get(struct device *dev, const char *id)
mutex_lock(&clocks_mutex);
list_for_each_entry(p, &clocks, node) {
if (p->id == idno &&
strcmp(id, p->name) == 0 && try_module_get(p->owner)) {
if (p->id == idno && strcmp(id, p->name) == 0) {
clk = p;
goto found;
}
}
list_for_each_entry(p, &clocks, node) {
if (strcmp(id, p->name) == 0 && try_module_get(p->owner)) {
if (strcmp(id, p->name) == 0) {
clk = p;
break;
}
......@@ -83,8 +220,13 @@ int clk_enable(struct clk *clk)
return -EINVAL;
spin_lock_irqsave(&clockfw_lock, flags);
if (arch_clock->clk_enable)
if (arch_clock->clk_enable) {
ret = arch_clock->clk_enable(clk);
if (ret == 0 && clk->flags & RECALC_ON_ENABLE)
_do_propagate_rate(clk, clk->parent->rate,
CURRENT_RATE);
}
spin_unlock_irqrestore(&clockfw_lock, flags);
return ret;
......@@ -106,30 +248,18 @@ void clk_disable(struct clk *clk)
goto out;
}
if (arch_clock->clk_disable)
if (arch_clock->clk_disable) {
arch_clock->clk_disable(clk);
if (clk->flags & RECALC_ON_ENABLE)
_do_propagate_rate(clk, clk->parent->rate,
CURRENT_RATE);
}
out:
spin_unlock_irqrestore(&clockfw_lock, flags);
}
EXPORT_SYMBOL(clk_disable);
int clk_get_usecount(struct clk *clk)
{
unsigned long flags;
int ret = 0;
if (clk == NULL || IS_ERR(clk))
return 0;
spin_lock_irqsave(&clockfw_lock, flags);
ret = clk->usecount;
spin_unlock_irqrestore(&clockfw_lock, flags);
return ret;
}
EXPORT_SYMBOL(clk_get_usecount);
unsigned long clk_get_rate(struct clk *clk)
{
unsigned long flags;
......@@ -148,8 +278,6 @@ EXPORT_SYMBOL(clk_get_rate);
void clk_put(struct clk *clk)
{
if (clk && !IS_ERR(clk))
module_put(clk->owner);
}
EXPORT_SYMBOL(clk_put);
......@@ -183,8 +311,14 @@ int clk_set_rate(struct clk *clk, unsigned long rate)
return ret;
spin_lock_irqsave(&clockfw_lock, flags);
if (arch_clock->clk_set_rate)
if (arch_clock->clk_set_rate) {
ret = arch_clock->clk_set_rate(clk, rate);
if (ret == 0)
_do_propagate_rate(clk, clk->parent->rate,
CURRENT_RATE);
}
spin_unlock_irqrestore(&clockfw_lock, flags);
return ret;
......@@ -194,14 +328,25 @@ EXPORT_SYMBOL(clk_set_rate);
int clk_set_parent(struct clk *clk, struct clk *parent)
{
unsigned long flags;
struct clk *prev_parent;
int ret = -EINVAL;
if (clk == NULL || IS_ERR(clk) || parent == NULL || IS_ERR(parent))
return ret;
spin_lock_irqsave(&clockfw_lock, flags);
if (arch_clock->clk_set_parent)
ret = arch_clock->clk_set_parent(clk, parent);
if (arch_clock->clk_set_parent) {
prev_parent = clk->parent;
ret = arch_clock->clk_set_parent(clk, parent);
if (ret == 0) {
omap_clk_del_child(prev_parent, clk);
omap_clk_add_child(parent, clk);
_do_propagate_rate(clk, clk->parent->rate,
CURRENT_RATE);
}
}
spin_unlock_irqrestore(&clockfw_lock, flags);
return ret;
......@@ -250,30 +395,30 @@ static int __init omap_clk_setup(char *str)
__setup("mpurate=", omap_clk_setup);
/* Used for clocks that always have same value as the parent clock */
void followparent_recalc(struct clk *clk)
void followparent_recalc(struct clk *clk, unsigned long new_parent_rate,
u8 rate_storage)
{
if (clk == NULL || IS_ERR(clk))
return;
clk->rate = clk->parent->rate;
if (unlikely(clk->flags & RATE_PROPAGATES))
propagate_rate(clk);
if (rate_storage == CURRENT_RATE)
clk->rate = new_parent_rate;
else if (rate_storage == TEMP_RATE)
clk->temp_rate = new_parent_rate;
}
/* Propagate rate to children */
void propagate_rate(struct clk * tclk)
void propagate_rate(struct clk *tclk, u8 rate_storage)
{
struct clk *clkp;
unsigned long parent_rate = 0;
if (tclk == NULL || IS_ERR(tclk))
return;
list_for_each_entry(clkp, &clocks, node) {
if (likely(clkp->parent != tclk))
continue;
if (likely((u32)clkp->recalc))
clkp->recalc(clkp);
}
if (rate_storage == CURRENT_RATE)
parent_rate = tclk->rate;
else if (rate_storage == TEMP_RATE)
parent_rate = tclk->temp_rate;
omap_clk_for_each_child(tclk, parent_rate, rate_storage,
_do_propagate_rate);
}
/**
......@@ -287,34 +432,53 @@ void recalculate_root_clocks(void)
{
struct clk *clkp;
list_for_each_entry(clkp, &clocks, node) {
if (unlikely(!clkp->parent) && likely((u32)clkp->recalc))
clkp->recalc(clkp);
}
list_for_each_entry(clkp, &clocks, node)
if (unlikely(!clkp->parent))
_do_propagate_rate(clkp, 0, CURRENT_RATE);
}
int clk_register(struct clk *clk)
{
int ret;
if (clk == NULL || IS_ERR(clk))
return -EINVAL;
mutex_lock(&clocks_mutex);
if (arch_clock->clk_register) {
ret = arch_clock->clk_register(clk);
if (ret)
goto cr_out;
}
list_add(&clk->node, &clocks);
if (!clk->children.next)
INIT_LIST_HEAD(&clk->children);
if (clk->parent)
omap_clk_add_child(clk->parent, clk);
if (clk->init)
clk->init(clk);
ret = 0;
cr_out:
mutex_unlock(&clocks_mutex);
return 0;
return ret;
}
EXPORT_SYMBOL(clk_register);
void clk_unregister(struct clk *clk)
{
struct clk_child *child, *tmp;
if (clk == NULL || IS_ERR(clk))
return;
mutex_lock(&clocks_mutex);
list_del(&clk->node);
if (clk->parent)
omap_clk_del_child(clk->parent, clk);
list_for_each_entry_safe(child, tmp, &clk->children, node)
if (child->flags & CLK_CHILD_SLAB_ALLOC)
kfree(child);
mutex_unlock(&clocks_mutex);
}
EXPORT_SYMBOL(clk_unregister);
......
......@@ -279,10 +279,7 @@ void omap_set_dma_transfer_params(int lch, int data_type, int elem_count,
val = dma_read(CCR(lch));
val &= ~(3 << 19);
if (dma_trigger > 63)
val |= 1 << 20;
if (dma_trigger > 31)
val |= 1 << 19;
val |= ((dma_trigger & ~(0x1f)) << 14);
val &= ~(0x1f);
val |= (dma_trigger & 0x1f);
......@@ -2420,6 +2417,19 @@ static int __init omap_init_dma(void)
if (cpu_class_is_omap2())
setup_irq(INT_24XX_SDMA_IRQ0, &omap24xx_dma_irq);
/* Enable smartidle idlemodes and autoidle */
if (cpu_is_omap34xx()) {
u32 v = dma_read(OCP_SYSCONFIG);
v &= ~(DMA_SYSCONFIG_MIDLEMODE_MASK |
DMA_SYSCONFIG_SIDLEMODE_MASK |
DMA_SYSCONFIG_AUTOIDLE);
v |= (DMA_SYSCONFIG_MIDLEMODE(DMA_IDLEMODE_SMARTIDLE) |
DMA_SYSCONFIG_SIDLEMODE(DMA_IDLEMODE_SMARTIDLE) |
DMA_SYSCONFIG_AUTOIDLE);
dma_write(v , OCP_SYSCONFIG);
}
/* FIXME: Update LCD DMA to work on 24xx */
if (cpu_class_is_omap1()) {
r = request_irq(INT_DMA_LCD, lcd_dma_irq_handler, 0,
......
......@@ -320,11 +320,9 @@ static void omap_dm_timer_reset(struct omap_dm_timer *timer)
l |= 0x2 << 8; /* Set clock activity to perserve f-clock on idle */
/*
* Enable wake-up only for GPT1 on OMAP2 CPUs.
* FIXME: All timers should have wake-up enabled and clear
* PRCM status.
* Enable wake-up on OMAP2 CPUs.
*/
if (cpu_class_is_omap2() && (timer == &dm_timers[0]))
if (cpu_class_is_omap2())
l |= 1 << 2;
omap_dm_timer_write_reg(timer, OMAP_TIMER_OCP_CFG_REG, l);
......
......@@ -20,8 +20,8 @@ struct clockdomain;
#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
struct clksel_rate {
u8 div;
u32 val;
u8 div;
u8 flags;
};
......@@ -31,56 +31,71 @@ struct clksel {
};
struct dpll_data {
u16 mult_div1_reg;
u32 mult_mask;
u32 div1_mask;
u16 last_rounded_m;
u8 last_rounded_n;
unsigned long last_rounded_rate;
unsigned int rate_tolerance;
u16 max_multiplier;
u8 min_divider;
u8 max_divider;
u32 max_tolerance;
struct clk *bypass_clk;
u16 control_reg;
u32 enable_mask;
u16 mult_div1_reg;
u16 control_reg;
u16 max_multiplier;
u16 last_rounded_m;
u8 last_rounded_n;
u8 min_divider;
u8 max_divider;
# if defined(CONFIG_ARCH_OMAP3)
u16 idlest_reg;
u32 idlest_mask;
u32 freqsel_mask;
u8 modes;
u8 auto_recal_bit;
u8 recal_en_bit;
u8 recal_st_bit;
u16 autoidle_reg;
u16 idlest_reg;
u32 autoidle_mask;
u32 idlest_mask;
u32 freqsel_mask;
# endif
};
#endif
/**
* struct clk_child - used to track the children of a clock
* @clk: child struct clk *
* @node: list_head
* @flags: is this entry allocated in bootmem or slab? is it deleted?
*
* One struct clk_child is allocated for each child clock @clk of a
* parent clock. @flags values are listed below and start with CLK_CHILD_*.
*/
struct clk_child {
struct clk *clk;
struct list_head node;
u8 flags;
};
struct clk {
struct list_head node;
struct module *owner;
const char *name;
int id;
struct clk *parent;
unsigned long rate;
unsigned long temp_rate;
struct list_head children;
__u32 flags;
u32 enable_reg;
__u8 enable_bit;
__s8 usecount;
u8 idlest_bit;
void (*recalc)(struct clk *);
void (*recalc)(struct clk *, unsigned long, u8);
int (*set_rate)(struct clk *, unsigned long);
long (*round_rate)(struct clk *, unsigned long);
void (*init)(struct clk *);
int (*enable)(struct clk *);
void (*disable)(struct clk *);
__u8 enable_bit;
__s8 usecount;
u8 idlest_bit;
#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
u8 fixed_div;
u16 clksel_reg;
u32 clksel_mask;
const struct clksel *clksel;
struct dpll_data *dpll_data;
......@@ -88,6 +103,7 @@ struct clk {
const char *name;
struct clockdomain *ptr;
} clkdm;
u16 clksel_reg;
s16 prcm_mod;
#else
__u8 rate_offset;
......@@ -101,6 +117,7 @@ struct clk {
struct cpufreq_frequency_table;
struct clk_functions {
int (*clk_register)(struct clk *clk);
int (*clk_enable)(struct clk *clk);
void (*clk_disable)(struct clk *clk);
long (*clk_round_rate)(struct clk *clk, unsigned long rate);
......@@ -120,33 +137,34 @@ extern unsigned int mpurate;
extern int clk_init(struct clk_functions *custom_clocks);
extern int clk_register(struct clk *clk);
extern void clk_unregister(struct clk *clk);
extern void propagate_rate(struct clk *clk);
extern void propagate_rate(struct clk *clk, u8 rate_storage);
extern void recalculate_root_clocks(void);
extern void followparent_recalc(struct clk *clk);
extern void followparent_recalc(struct clk *clk, unsigned long parent_rate,
u8 rate_storage);
extern void clk_allow_idle(struct clk *clk);
extern void clk_deny_idle(struct clk *clk);
extern int clk_get_usecount(struct clk *clk);
extern void clk_enable_init_clocks(void);
#ifdef CONFIG_CPU_FREQ
extern void clk_init_cpufreq_table(struct cpufreq_frequency_table **table);
#endif
void omap_clk_add_child(struct clk *clk, struct clk *clk2);
void omap_clk_del_child(struct clk *clk, struct clk *clk2);
/* Clock flags */
#define RATE_CKCTL (1 << 0) /* Main fixed ratio clocks */
#define RATE_FIXED (1 << 1) /* Fixed clock rate */
#define RATE_PROPAGATES (1 << 2) /* Program children too */
#define VIRTUAL_CLOCK (1 << 3) /* Composite clock from table */
/* bits 1-3 are currently free */
#define ALWAYS_ENABLED (1 << 4) /* Clock cannot be disabled */
#define ENABLE_REG_32BIT (1 << 5) /* Use 32-bit access */
/* bit 6 is currently free */
#define CLOCK_IDLE_CONTROL (1 << 7)
#define CLOCK_NO_IDLE_PARENT (1 << 8)
#define DELAYED_APP (1 << 9) /* Delay application of clock */
#define CONFIG_PARTICIPANT (1 << 10) /* Fundamental clock */
/* bit 10 is currently free */
#define ENABLE_ON_INIT (1 << 11) /* Enable upon framework init */
#define INVERT_ENABLE (1 << 12) /* 0 enables, 1 disables */
#define WAIT_READY (1 << 13) /* wait for dev to leave idle */
/* bits 14-20 are currently free */
#define RECALC_ON_ENABLE (1 << 14) /* recalc/prop on ena/disa */
/* bits 15-20 are currently free */
#define CLOCK_IN_OMAP310 (1 << 21)
#define CLOCK_IN_OMAP730 (1 << 22)
#define CLOCK_IN_OMAP1510 (1 << 23)
......@@ -167,6 +185,14 @@ extern void clk_init_cpufreq_table(struct cpufreq_frequency_table **table);
#define RATE_IN_24XX (RATE_IN_242X | RATE_IN_243X)
/* rate_storage parameter flags */
#define CURRENT_RATE 0
#define TEMP_RATE 1
/* clk_child flags */
#define CLK_CHILD_SLAB_ALLOC (1 << 0) /* if !set, bootmem was used */
#define CLK_CHILD_DELETED (1 << 1) /* can be reused */
/*
* clk.prcm_mod flags (possible since only the top byte in clk.prcm_mod
* is significant)
......
......@@ -33,8 +33,6 @@ struct sys_timer;
extern void omap_map_common_io(void);
extern struct sys_timer omap_timer;
extern void omap_serial_init(void);
extern void omap_serial_enable_clocks(int enable);
#ifdef CONFIG_I2C_OMAP
extern int omap_register_i2c_bus(int bus_id, u32 clkrate,
struct i2c_board_info const *info,
......
......@@ -208,6 +208,15 @@
#define OMAP2_PBIASLITEPWRDNZ0 (1 << 1)
#define OMAP2_PBIASLITEVMODE0 (1 << 0)
/* CONTROL_PADCONF_X bits */
#define OMAP3_PADCONF_WAKEUPEVENT0 (1 << 15)
#define OMAP3_PADCONF_WAKEUPENABLE0 (1 << 14)
/* CONTROL_IVA2_BOOTMOD bits */
#define OMAP3_IVA2_BOOTMOD_SHIFT 0
#define OMAP3_IVA2_BOOTMOD_MASK (0xf << 0)
#define OMAP3_IVA2_BOOTMOD_IDLE (0x1 << 0)
#ifndef __ASSEMBLY__
#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
extern void __iomem *omap_ctrl_base_get(void);
......
......@@ -387,6 +387,21 @@
#define DMA_THREAD_FIFO_25 (0x02 << 14)
#define DMA_THREAD_FIFO_50 (0x03 << 14)
/* DMA4_OCP_SYSCONFIG bits */
#define DMA_SYSCONFIG_MIDLEMODE_MASK (3 << 12)
#define DMA_SYSCONFIG_CLOCKACTIVITY_MASK (3 << 8)
#define DMA_SYSCONFIG_EMUFREE (1 << 5)
#define DMA_SYSCONFIG_SIDLEMODE_MASK (3 << 3)
#define DMA_SYSCONFIG_SOFTRESET (1 << 2)
#define DMA_SYSCONFIG_AUTOIDLE (1 << 0)
#define DMA_SYSCONFIG_MIDLEMODE(n) ((n) << 12)
#define DMA_SYSCONFIG_SIDLEMODE(n) ((n) << 3)
#define DMA_IDLEMODE_SMARTIDLE 0x2
#define DMA_IDLEMODE_NO_IDLE 0x1
#define DMA_IDLEMODE_FORCE_IDLE 0x0
/* Chaining modes*/
#ifndef CONFIG_ARCH_OMAP1
#define OMAP_DMA_STATIC_CHAIN 0x1
......
......@@ -87,16 +87,6 @@ extern void omap_set_gpio_debounce_time(int gpio, int enable);
#include <linux/errno.h>
#include <asm-generic/gpio.h>
static inline int omap_request_gpio(int gpio)
{
return gpio_request(gpio, "FIXME");
}
static inline void omap_free_gpio(int gpio)
{
gpio_free(gpio);
}
static inline int gpio_get_value(unsigned gpio)
{
return __gpio_get_value(gpio);
......
......@@ -33,6 +33,9 @@ struct omap_mbox_ops {
void (*disable_irq)(struct omap_mbox *mbox, omap_mbox_irq_t irq);
void (*ack_irq)(struct omap_mbox *mbox, omap_mbox_irq_t irq);
int (*is_irq)(struct omap_mbox *mbox, omap_mbox_irq_t irq);
/* ctx */
void (*save_ctx)(struct omap_mbox *mbox);
void (*restore_ctx)(struct omap_mbox *mbox);
};
struct omap_mbox_queue {
......@@ -53,7 +56,7 @@ struct omap_mbox {
mbox_msg_t seq_snd, seq_rcv;
struct device dev;
struct device *dev;
struct omap_mbox *next;
void *priv;
......@@ -61,15 +64,33 @@ struct omap_mbox {
void (*err_notify)(void);
};
extern struct omap_mbox mbox_dsp_info;
int omap_mbox_msg_send(struct omap_mbox *, mbox_msg_t msg, void *);
void omap_mbox_init_seq(struct omap_mbox *);
struct omap_mbox *omap_mbox_get(const char *);
void omap_mbox_put(struct omap_mbox *);
int omap_mbox_register(struct omap_mbox *);
int omap_mbox_register(struct device *parent, struct omap_mbox *);
int omap_mbox_unregister(struct omap_mbox *);
static inline void omap_mbox_save_ctx(struct omap_mbox *mbox)
{
if (!mbox->ops->save_ctx) {
dev_err(mbox->dev, "%s:\tno save\n", __func__);
return;
}
mbox->ops->save_ctx(mbox);
}
static inline void omap_mbox_restore_ctx(struct omap_mbox *mbox)
{
if (!mbox->ops->restore_ctx) {
dev_err(mbox->dev, "%s:\tno restore\n", __func__);
return;
}
mbox->ops->restore_ctx(mbox);
}
#endif /* MAILBOX_H */
......@@ -790,6 +790,12 @@ enum omap34xx_index {
*/
AH8_34XX_GPIO29,
J25_34XX_GPIO170,
AF26_34XX_GPIO0,
AF22_34XX_GPIO9,
AF6_34XX_GPIO140_UP,
AE6_34XX_GPIO141,
AF5_34XX_GPIO142,
AE5_34XX_GPIO143
};
struct omap_mux_cfg {
......
......@@ -56,6 +56,9 @@
#define OMAP34XX_SR1_BASE 0x480C9000
#define OMAP34XX_SR2_BASE 0x480CB000
#define OMAP34XX_CAMERA_BASE (L4_34XX_BASE + 0xBC000)
#define OMAP34XX_MAILBOX_BASE (L4_34XX_BASE + 0x94000)
#if defined(CONFIG_ARCH_OMAP3430)
......@@ -63,7 +66,6 @@
#define OMAP2_CM_BASE OMAP3430_CM_BASE
#define OMAP2_PRM_BASE OMAP3430_PRM_BASE
#define OMAP2_VA_IC_BASE IO_ADDRESS(OMAP34XX_IC_BASE)
#define OMAP34XX_CAMERA_BASE (L4_34XX_BASE + 0xBC000)
#endif
......
......@@ -40,4 +40,13 @@
__ret; \
})
#ifndef __ASSEMBLER__
extern void omap_serial_init(void);
extern int omap_uart_can_sleep(void);
extern void omap_uart_check_wakeup(void);
extern void omap_uart_prepare_suspend(void);
extern void omap_uart_prepare_idle(int num);
extern void omap_uart_resume_idle(int num);
#endif
#endif
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......@@ -77,38 +77,6 @@
/*-------------------------------------------------------------------------*/
#if defined(CONFIG_ARCH_OMAP_OTG) || defined(CONFIG_USB_MUSB_OTG)
static struct otg_transceiver *xceiv;
/**
* otg_get_transceiver - find the (single) OTG transceiver driver
*
* Returns the transceiver driver, after getting a refcount to it; or
* null if there is no such transceiver. The caller is responsible for
* releasing that count.
*/
struct otg_transceiver *otg_get_transceiver(void)
{
if (xceiv)
get_device(xceiv->dev);
return xceiv;
}
EXPORT_SYMBOL(otg_get_transceiver);
int otg_set_transceiver(struct otg_transceiver *x)
{
if (xceiv && x)
return -EBUSY;
xceiv = x;
return 0;
}
EXPORT_SYMBOL(otg_set_transceiver);
#endif
/*-------------------------------------------------------------------------*/
#if defined(CONFIG_ARCH_OMAP_OTG) || defined(CONFIG_ARCH_OMAP15XX)
static void omap2_usb_devconf_clear(u8 port, u32 mask)
......
......@@ -13,7 +13,7 @@
#include <linux/mtd/partitions.h>
#include <linux/mtd/physmap.h>
#include <asm/arch/smc.h>
#include <mach/smc.h>
static struct smc_timing flash_timing __initdata = {
.ncs_read_setup = 0,
......
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......@@ -10,7 +10,7 @@ MKIMAGE := $(srctree)/scripts/mkuboot.sh
extra-y := vmlinux.bin vmlinux.gz
OBJCOPYFLAGS_vmlinux.bin := -O binary
OBJCOPYFLAGS_vmlinux.bin := -O binary -R .note.gnu.build-id
$(obj)/vmlinux.bin: vmlinux FORCE
$(call if_changed,objcopy)
......
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