i965_drv_video: PCI IDs and new MI_FLUSH_DW command for Sandybridge

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>

i965_drv_video/i965_defines.h

@@ -380,6 +380,8 @@
 #define IEF_FILTER_SIZE_3X3             0
 #define IEF_FILTER_SIZE_5X5             1
 
-#define URB_SIZE(intel)         (IS_IRONLAKE(intel->device_id) ? 1024 : \
+#define URB_SIZE(intel)         (IS_GEN6(intel->device_id) ? 1024 :     \
+                                 IS_IRONLAKE(intel->device_id) ? 1024 : \
                                  IS_G4X(intel->device_id) ? 384 : 256)
+
 #endif /* _I965_DEFINES_H_ */

i965_drv_video/i965_drv_video.c

@@ -1252,7 +1252,8 @@ i965_Init(VADriverContextP ctx)
         return VA_STATUS_ERROR_UNKNOWN;
 
     if (!IS_G4X(i965->intel.device_id) &&
-        !IS_IRONLAKE(i965->intel.device_id))
+        !IS_IRONLAKE(i965->intel.device_id) &&
+        !IS_GEN6(i965->intel.device_id))
         return VA_STATUS_ERROR_UNKNOWN;
 
     if (i965_media_init(ctx) == False)

i965_drv_video/intel_batchbuffer.c

@@ -281,21 +281,12 @@ intel_batchbuffer_data_bcs(VADriverContextP ctx, void *data, unsigned int size)
     intel_batchbuffer_data_helper(ctx, intel->batch_bcs, data, size);
 }
 
-static void
-intel_batchbuffer_emit_mi_flush_helper(VADriverContextP ctx,
-                                       struct intel_batchbuffer *batch)
-{
-    intel_batchbuffer_require_space_helper(ctx, batch, 4);
-    intel_batchbuffer_emit_dword_helper(batch, 
-                                        MI_FLUSH | STATE_INSTRUCTION_CACHE_INVALIDATE);
-}
-
 void
 intel_batchbuffer_emit_mi_flush(VADriverContextP ctx)
 {
-    struct intel_driver_data *intel = intel_driver_data(ctx);
-
-    intel_batchbuffer_emit_mi_flush_helper(ctx, intel->batch);
+    BEGIN_BATCH(ctx, 1);
+    OUT_BATCH(ctx, MI_FLUSH | MI_FLUSH_STATE_INSTRUCTION_CACHE_INVALIDATE);
+    ADVANCE_BATCH(ctx);
 }
 
 void
@@ -303,7 +294,18 @@ intel_batchbuffer_emit_mi_flush_bcs(VADriverContextP ctx)
 {
     struct intel_driver_data *intel = intel_driver_data(ctx);
 
-    intel_batchbuffer_emit_mi_flush_helper(ctx, intel->batch_bcs);
+    if (IS_GEN6(intel->device_id)) {
+        BEGIN_BCS_BATCH(ctx, 4);
+        OUT_BCS_BATCH(ctx, MI_FLUSH_DW | MI_FLUSH_DW_VIDEO_PIPELINE_CACHE_INVALIDATE);
+        OUT_BCS_BATCH(ctx, 0);
+        OUT_BCS_BATCH(ctx, 0);
+        OUT_BCS_BATCH(ctx, 0);
+        ADVANCE_BCS_BATCH(ctx);
+    } else {
+        BEGIN_BCS_BATCH(ctx, 1);
+        OUT_BCS_BATCH(ctx, MI_FLUSH | MI_FLUSH_STATE_INSTRUCTION_CACHE_INVALIDATE);
+        ADVANCE_BCS_BATCH(ctx);
+    }
 }
 
 void

i965_drv_video/intel_driver.h

@@ -29,7 +29,10 @@
 #define MI_BATCH_BUFFER_START                   (CMD_MI | (0x31 << 23))
 
 #define MI_FLUSH                                (CMD_MI | (0x4 << 23))
-#define STATE_INSTRUCTION_CACHE_INVALIDATE      (0x1 << 0)
+#define   MI_FLUSH_STATE_INSTRUCTION_CACHE_INVALIDATE   (0x1 << 0)
+
+#define MI_FLUSH_DW                             (CMD_MI | (0x26 << 23) | 0x2)
+#define   MI_FLUSH_DW_VIDEO_PIPELINE_CACHE_INVALIDATE   (0x1 << 7)
 
 #define XY_COLOR_BLT_CMD                        (CMD_2D | (0x50 << 22) | 0x04)
 #define XY_COLOR_BLT_WRITE_ALPHA                (1 << 21)
@@ -124,9 +127,20 @@ struct intel_region
 #define PCI_CHIP_IRONLAKE_D_G           0x0042
 #define PCI_CHIP_IRONLAKE_M_G           0x0046
 
-#define IS_G45(devid)           (devid == PCI_CHIP_IGD_E_G || \
-                                 devid == PCI_CHIP_Q45_G || \
-                                 devid == PCI_CHIP_G45_G || \
+#ifndef PCI_CHIP_SANDYBRIDGE_GT1
+#define PCI_CHIP_SANDYBRIDGE_GT1	0x0102  /* Desktop */
+#define PCI_CHIP_SANDYBRIDGE_GT2	0x0112
+#define PCI_CHIP_SANDYBRIDGE_GT2_PLUS	0x0122
+#define PCI_CHIP_SANDYBRIDGE_M_GT1	0x0106  /* Mobile */
+#define PCI_CHIP_SANDYBRIDGE_M_GT2	0x0116
+#define PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS	0x0126
+#define PCI_CHIP_SANDYBRIDGE_S_GT	0x010A  /* Server */
+#endif
+
+
+#define IS_G45(devid)           (devid == PCI_CHIP_IGD_E_G ||   \
+                                 devid == PCI_CHIP_Q45_G ||     \
+                                 devid == PCI_CHIP_G45_G ||     \
                                  devid == PCI_CHIP_G41_G)
 #define IS_GM45(devid)          (devid == PCI_CHIP_GM45_GM)
 #define IS_G4X(devid)		(IS_G45(devid) || IS_GM45(devid))
@@ -135,4 +149,12 @@ struct intel_region
 #define IS_IRONLAKE_M(devid)    (devid == PCI_CHIP_IRONLAKE_M_G)
 #define IS_IRONLAKE(devid)      (IS_IRONLAKE_D(devid) || IS_IRONLAKE_M(devid))
 
+#define IS_GEN6(devid)          (devid == PCI_CHIP_SANDYBRIDGE_GT1 || \
+                                 devid == PCI_CHIP_SANDYBRIDGE_GT2 || \
+                                 devid == PCI_CHIP_SANDYBRIDGE_GT2_PLUS ||\
+                                 devid == PCI_CHIP_SANDYBRIDGE_M_GT1 || \
+                                 devid == PCI_CHIP_SANDYBRIDGE_M_GT2 || \
+                                 devid == PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS || \
+                                 devid == PCI_CHIP_SANDYBRIDGE_S_GT)
+
 #endif /* _INTEL_DRIVER_H_ */