Commit addedfb4 authored by Xiang, Haihao's avatar Xiang, Haihao

i965_drv_video: fix VME shaders

1. The response length for inter type on Ivybridge is 6.
2. fix register region
Signed-off-by: default avatarXiang, Haihao <haihao.xiang@intel.com>
parent 17be8ff5
......@@ -148,6 +148,8 @@ define(`msg_reg4', `m4') /* m4 */
* VME message payload
*/
define(`vme_msg_length', `4')
define(`vme_intra_wb_length', `1')
define(`vme_inter_wb_length', `4')
define(`vme_msg_ind', `msg_ind')
define(`vme_msg_0', `msg_reg0')
define(`vme_msg_1', `msg_reg1')
......
......@@ -150,6 +150,8 @@ define(`msg_reg4', `g68')
* VME message payload
*/
define(`vme_msg_length', `5')
define(`vme_intra_wb_length', `1')
define(`vme_inter_wb_length', `6')
define(`vme_msg_ind', `msg_ind')
define(`vme_msg_0', `msg_reg0')
define(`vme_msg_1', `msg_reg1')
......
......@@ -28,7 +28,7 @@ mov (16) tmp_reg2.0<1>:UD 0x0:UD {align1};
/* m0 */
mul (2) tmp_reg0.8<1>:UW orig_xy_ub<2,2,1>:UB 16:UW {align1}; /* Source = (x, y) * 16 */
mul (2) tmp_reg0.0<1>:UW orig_xy_ub<2,2,1>:UB 16:UW {align1};
add (2) tmp_reg0.0<1>:W tmp_reg0.0<2,2,1>:W -8:W {align1}; /* Reference = (x-8,y-8)-(x+24,y+24) */
add (2) tmp_reg0.0<1>:W tmp_reg0.0<2,2,1>:W -8:W {align1}; /* Reference = (x-8,y-8)-(x+24,y+24) */
mov (1) tmp_reg0.12<1>:UD INTER_PART_MASK + INTER_SAD_HAAR + SUB_PEL_MODE_QUARTER:UD {align1}; /* 16x16 Source, 1/4 pixel, harr */
mov (1) tmp_reg0.20<1>:UB thread_id_ub {align1}; /* dispatch id */
......@@ -37,7 +37,7 @@ mov (8) vme_msg_0.0<1>:UD tmp_reg0.0<8,8,1>:UD {align1};
/* m1 */
mov (1) tmp_reg1.4<1>:UD MAX_NUM_MV:UD {align1}; /* Default value MAX 32 MVs */
mov (1) tmp_reg1.8<1>:UD SEARCH_PATH_LEN:UD {align1};
mov (1) tmp_reg1.8<1>:UD SEARCH_PATH_LEN:UD {align1};
mov (8) vme_msg_1<1>:UD tmp_reg1.0<8,8,1>:UD {align1};
......@@ -61,7 +61,7 @@ send (8)
VME_MESSAGE_TYPE_INTER
)
mlen vme_msg_length
rlen 4
rlen vme_inter_wb_length
{align1};
/*
......@@ -74,7 +74,7 @@ mov (1) tmp_reg3.20<1>:UB thread_id_ub {align1}; /* dispa
mov (8) msg_reg0.0<1>:UD tmp_reg3.0<8,8,1>:UD {align1};
mov (2) tmp_reg3.0<1>:UW vme_wb1.0<2,2,1>:UB {align1};
add (2) tmp_reg3.0<1>:W tmp_reg3.0<16,16,1>:W -32:W {align1};
add (2) tmp_reg3.0<1>:W tmp_reg3.0<2,2,1>:W -32:W {align1};
mov (8) msg_reg1.0<1>:UD tmp_reg3.0<8,8,0>:UD {align1};
......
......@@ -20,7 +20,7 @@
{ 0x00000001, 0x24740231, 0x00000014, 0x00000000 },
{ 0x00600001, 0x20000022, 0x008d0460, 0x00000000 },
{ 0x00200001, 0x24600229, 0x004501a0, 0x00000000 },
{ 0x00200040, 0x24603dad, 0x00b10460, 0xffe0ffe0 },
{ 0x00200040, 0x24603dad, 0x00450460, 0xffe0ffe0 },
{ 0x00600001, 0x20200022, 0x008c0460, 0x00000000 },
{ 0x00600001, 0x20400022, 0x008c0460, 0x00000000 },
{ 0x05800031, 0x22001cdd, 0x00000000, 0x061b0303 },
......
......@@ -13,14 +13,14 @@
{ 0x00600001, 0x28400061, 0x00000000, 0x00000000 },
{ 0x00600001, 0x28600061, 0x00000000, 0x00000000 },
{ 0x00600001, 0x28800061, 0x00000000, 0x00000000 },
{ 0x08600031, 0x21801cbd, 0x00000800, 0x0a482001 },
{ 0x08600031, 0x21801cbd, 0x00000800, 0x0a682001 },
{ 0x00000041, 0x24684521, 0x000000a2, 0x000000a1 },
{ 0x00000040, 0x24684421, 0x00000468, 0x000000a0 },
{ 0x00000041, 0x24680c21, 0x00000468, 0x00000004 },
{ 0x00000001, 0x24740231, 0x00000014, 0x00000000 },
{ 0x00600001, 0x28000021, 0x008d0460, 0x00000000 },
{ 0x00200001, 0x24600229, 0x004501a0, 0x00000000 },
{ 0x00200040, 0x24603dad, 0x00b10460, 0xffe0ffe0 },
{ 0x00200040, 0x24603dad, 0x00450460, 0xffe0ffe0 },
{ 0x00600001, 0x28200021, 0x008c0460, 0x00000000 },
{ 0x00600001, 0x28400021, 0x008c0460, 0x00000000 },
{ 0x0a800031, 0x20001cac, 0x00000800, 0x060a0300 },
......
......@@ -91,7 +91,7 @@ send (8)
VME_MESSAGE_TYPE_INTRA
)
mlen vme_msg_length
rlen 1
rlen vme_intra_wb_length
{align1};
/*
......
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