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videolan
libva
Commits
85e330ce
Commit
85e330ce
authored
Apr 21, 2011
by
Xiang, Haihao
Browse files
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Browse Files
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Email Patches
Plain Diff
i965_drv_video/encode: fetch neighbor pixel in intra shader
Signed-off-by:
Xiang, Haihao
<
haihao.xiang@intel.com
>
parent
48b03c4a
Changes
3
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Showing
3 changed files
with
265 additions
and
25 deletions
+265
-25
i965_drv_video/gen6_vme.c
i965_drv_video/gen6_vme.c
+69
-1
i965_drv_video/shaders/vme/intra_frame.asm
i965_drv_video/shaders/vme/intra_frame.asm
+158
-17
i965_drv_video/shaders/vme/intra_frame.g6b
i965_drv_video/shaders/vme/intra_frame.g6b
+38
-7
No files found.
i965_drv_video/gen6_vme.c
View file @
85e330ce
...
@@ -75,6 +75,25 @@ static struct media_kernel gen6_vme_kernels[] = {
...
@@ -75,6 +75,25 @@ static struct media_kernel gen6_vme_kernels[] = {
#define GEN6_VME_KERNEL_NUMBER ARRAY_ELEMS(gen6_vme_kernels)
#define GEN6_VME_KERNEL_NUMBER ARRAY_ELEMS(gen6_vme_kernels)
static
void
gen6_vme_set_common_surface_tiling
(
struct
i965_surface_state
*
ss
,
unsigned
int
tiling
)
{
switch
(
tiling
)
{
case
I915_TILING_NONE
:
ss
->
ss3
.
tiled_surface
=
0
;
ss
->
ss3
.
tile_walk
=
0
;
break
;
case
I915_TILING_X
:
ss
->
ss3
.
tiled_surface
=
1
;
ss
->
ss3
.
tile_walk
=
I965_TILEWALK_XMAJOR
;
break
;
case
I915_TILING_Y
:
ss
->
ss3
.
tiled_surface
=
1
;
ss
->
ss3
.
tile_walk
=
I965_TILEWALK_YMAJOR
;
break
;
}
}
static
void
static
void
gen6_vme_set_source_surface_tiling
(
struct
i965_surface_state2
*
ss
,
unsigned
int
tiling
)
gen6_vme_set_source_surface_tiling
(
struct
i965_surface_state2
*
ss
,
unsigned
int
tiling
)
{
{
...
@@ -153,6 +172,53 @@ static void gen6_vme_source_surface_state(VADriverContextP ctx,
...
@@ -153,6 +172,53 @@ static void gen6_vme_source_surface_state(VADriverContextP ctx,
media_state
->
surface_state
[
index
].
bo
=
bo
;
media_state
->
surface_state
[
index
].
bo
=
bo
;
}
}
static
void
gen6_vme_media_source_surface_state
(
VADriverContextP
ctx
,
int
index
,
struct
object_surface
*
obj_surface
)
{
struct
i965_driver_data
*
i965
=
i965_driver_data
(
ctx
);
struct
gen6_media_state
*
media_state
=
&
i965
->
gen6_media_state
;
struct
i965_surface_state
*
ss
;
dri_bo
*
bo
;
int
w
,
h
,
w_pitch
;
unsigned
int
tiling
,
swizzle
;
w
=
obj_surface
->
orig_width
;
h
=
obj_surface
->
orig_height
;
w_pitch
=
obj_surface
->
width
;
/* Y plane */
dri_bo_get_tiling
(
obj_surface
->
bo
,
&
tiling
,
&
swizzle
);
bo
=
dri_bo_alloc
(
i965
->
intel
.
bufmgr
,
"surface state"
,
sizeof
(
struct
i965_surface_state
),
0x1000
);
assert
(
bo
);
dri_bo_map
(
bo
,
True
);
assert
(
bo
->
virtual
);
ss
=
bo
->
virtual
;
memset
(
ss
,
0
,
sizeof
(
*
ss
));
ss
->
ss0
.
surface_type
=
I965_SURFACE_2D
;
ss
->
ss0
.
surface_format
=
I965_SURFACEFORMAT_R8_UNORM
;
ss
->
ss1
.
base_addr
=
obj_surface
->
bo
->
offset
;
ss
->
ss2
.
width
=
w
/
4
-
1
;
ss
->
ss2
.
height
=
h
-
1
;
ss
->
ss3
.
pitch
=
w_pitch
-
1
;
gen6_vme_set_common_surface_tiling
(
ss
,
tiling
);
dri_bo_emit_reloc
(
bo
,
I915_GEM_DOMAIN_RENDER
,
0
,
0
,
offsetof
(
struct
i965_surface_state
,
ss1
),
obj_surface
->
bo
);
dri_bo_unmap
(
bo
);
assert
(
index
<
MAX_MEDIA_SURFACES_GEN6
);
media_state
->
surface_state
[
index
].
bo
=
bo
;
}
static
VAStatus
static
VAStatus
gen6_vme_output_buffer_setup
(
VADriverContextP
ctx
,
gen6_vme_output_buffer_setup
(
VADriverContextP
ctx
,
VAContextID
context
,
VAContextID
context
,
...
@@ -235,6 +301,8 @@ static VAStatus gen6_vme_surface_setup(VADriverContextP ctx,
...
@@ -235,6 +301,8 @@ static VAStatus gen6_vme_surface_setup(VADriverContextP ctx,
obj_surface
=
SURFACE
(
encode_state
->
current_render_target
);
obj_surface
=
SURFACE
(
encode_state
->
current_render_target
);
assert
(
obj_surface
);
assert
(
obj_surface
);
gen6_vme_source_surface_state
(
ctx
,
0
,
obj_surface
);
gen6_vme_source_surface_state
(
ctx
,
0
,
obj_surface
);
gen6_vme_media_source_surface_state
(
ctx
,
4
,
obj_surface
);
if
(
!
is_intra
)
{
if
(
!
is_intra
)
{
/* reference 0 */
/* reference 0 */
obj_surface
=
SURFACE
(
pPicParameter
->
reference_picture
);
obj_surface
=
SURFACE
(
pPicParameter
->
reference_picture
);
...
@@ -474,7 +542,7 @@ static int gen6_vme_media_object_intra(VADriverContextP ctx,
...
@@ -474,7 +542,7 @@ static int gen6_vme_media_object_intra(VADriverContextP ctx,
OUT_BATCH
(
ctx
,
0
);
OUT_BATCH
(
ctx
,
0
);
/*inline data */
/*inline data */
OUT_BATCH
(
ctx
,
0x00000000
);
/*M0.0 Refrence0 X,Y, not used in Intra*/
OUT_BATCH
(
ctx
,
mb_width
<<
16
|
mb_y
<<
8
|
mb_x
);
/*M0.0 Refrence0 X,Y, not used in Intra*/
OUT_BATCH
(
ctx
,
0x00000000
);
/*M0.1 Refrence1 X,Y, not used in Intra*/
OUT_BATCH
(
ctx
,
0x00000000
);
/*M0.1 Refrence1 X,Y, not used in Intra*/
OUT_BATCH
(
ctx
,
(
mb_y
<<
20
)
|
OUT_BATCH
(
ctx
,
(
mb_y
<<
20
)
|
(
mb_x
<<
4
));
/*M0.2 Source X,y*/
(
mb_x
<<
4
));
/*M0.2 Source X,y*/
...
...
i965_drv_video/shaders/vme/intra_frame.asm
View file @
85e330ce
...
@@ -17,24 +17,165 @@
...
@@ -17,24 +17,165 @@
include
(
`
vme_header.inc
'
)
include
(
`
vme_header.inc
'
)
/*
inline
input
data
:
r5~r11
*/
/*
mov
(
1
)
r5.20
<
1
>
:
UB
r0.20
<
1
,
1
,
0
>
:
UB
{
al
ign1
}
;
*
Constant
mov
(
8
)
m0.0
<
1
>
:
UD
r5.0
<
8
,
8
,
1
>
:
UD
{
al
ign1
}
;
*/
mov
(
8
)
m1.0
<
1
>
:
UD
r6.0
<
8
,
8
,
1
>
:
UD
{
al
ign1
}
;
define
(
`BLOCK_32X1', `
0x0000001F
'
)
mov
(
8
)
m2.0
<
1
>
:
UD
r7.0
<
8
,
8
,
1
>
:
UD
{
al
ign1
}
;
define
(
`BLOCK_4X16', `
0x000F0003
'
)
mov
(
8
)
m3.0
<
1
>
:
UD
r8.0
<
8
,
8
,
1
>
:
UD
{
al
ign1
}
;
send
(
8
)
0
r12
null
vme
(
0
,
0
,
0
,
2
)
mlen
4
rlen
1
{
al
ign1
}
;
define
(
`LUMA_INTRA_16x16_DISABLE', `
0x1
'
)
define
(
`LUMA_INTRA_8x8_DISABLE', `
0x2
'
)
mov
(
1
)
r9.20
<
1
>
:
UB
r0.20
<
1
,
1
,
0
>
:
UB
{
al
ign1
}
;
define
(
`LUMA_INTRA_4x4_DISABLE', `
0x4
'
)
mov
(
8
)
m0.0
<
1
>
:
UD
r9.0
<
8
,
8
,
1
>
:
UD
{
al
ign1
}
;
mov
(
1
)
m1.0
<
1
>
:
UD
r12.0
<
0
,
1
,
0
>
:
UD
{
al
ign1
}
; /*W0.0*/
define
(
`INTRA_PRED_AVAIL_FLAG_AE', `
0x60
'
)
mov
(
1
)
m1.4
<
1
>
:
UD
r12.16
<
0
,
1
,
0
>
:
UD
{
al
ign1
}
; /*W0.4*/
define
(
`INTRA_PRED_AVAIL_FLAG_B', `
0x10
'
)
mov
(
1
)
m1.8
<
1
>
:
UD
r12.20
<
0
,
1
,
0
>
:
UD
{
al
ign1
}
; /*W0.5*/
define
(
`INTRA_PRED_AVAIL_FLAG_C', `
0x8
'
)
mov
(
1
)
m1.12
<
1
>
:
UD
r12.24
<
0
,
1
,
0
>
:
UD
{
al
ign1
}
; /*W0.6*/
define
(
`INTRA_PRED_AVAIL_FLAG_D', `
0x4
'
)
define
(
`BIND_IDX_VME', `
0
'
)
define
(
`BIND_IDX_VME_REF0', `
1
'
)
define
(
`BIND_IDX_VME_REF1', `
2
'
)
define
(
`BIND_IDX_OUTPUT', `
3
'
)
define
(
`BIND_IDX_INEP', `
4
'
)
define
(
`INTRA_PREDICTORE_MODE', `
0x11111111
:
UD
'
)
/*
GRF
registers
*
r0
header
*
r1~r4
constant
buffer
*
r5~r8
inline
data
for
VME
message
*
r9
inline
data
for
Oword
Bl
ock
Write
message
*
r12
write
back
of
VME
message
*
r13
write
back
of
Oword
Bl
ock
Write
*/
/*
*
GRF
0
--
header
*/
define
(
`thread_id_ub', `
r0.20
<
0
,
1
,
0
>
:
UB
'
)
/*
thread
id
in
payload
*/
/*
*
GRF
5
--
inline
data
*/
define
(
`
inline_reg0
', `r5'
)
define
(
`
w_in_mb_uw
'
,
`
inline_reg0.2
'
)
define
(
`orig_xy_ub', `
inline_reg0.0
'
)
define
(
`orig_x_ub', `
inline_reg0.0
'
)
/*
in
macroblock
*/
define
(
`orig_y_ub', `
inline_reg0.1
'
)
define
(
`msg_reg0', `
m0
'
)
/*
m0
*/
define
(
`msg_reg1', `
m1
'
)
/*
m1
*/
define
(
`msg_reg2', `
m2
'
)
/*
m2
*/
define
(
`msg_reg3', `
m3
'
)
/*
m3
*/
define
(
`
vme_inline0
', `r5'
)
define
(
`
vme_inline1
', `r6'
)
define
(
`
vme_inline2
', `r7'
)
define
(
`
vme_inline3
', `r8'
)
define
(
`vme_wb', `
r12
'
)
/*
write
back
for
VME
*/
define
(
`obw_m0_8ud', `
m0.0
<
1
>
:
UD
'
)
/*
m0
*/
define
(
`obw_m1_0_1ud', `
m1.0
<
1
>
:
UD
'
)
/*
m1.0
*/
define
(
`obw_m1_4_1ud', `
m1.4
<
1
>
:
UD
'
)
/*
m1.4
*/
define
(
`obw_m1_8_1ud', `
m1.8
<
1
>
:
UD
'
)
/*
m1.8
*/
define
(
`obw_m1_12_1ud', `
m1.12
<
1
>
:
UD
'
)
/*
m1.12
*/
define
(
`
obw_inline0
', `r9'
)
define
(
`obw_wb', `
r13
'
)
/*
used
for
write
commit
in
Oword
Bl
ock
Write
*/
/*
*
Intra
Neighbor
Edge
Pixels
*/
define
(
`INEP_ROW', `
r14
'
)
define
(
`INEP_COL0', `
r16
'
)
define
(
`INEP_COL1', `
r17
'
)
/*
*
temporary
registers
*/
define
(
`tmp_reg0', `
r32
'
)
define
(
`tmp_reg1', `
r33
'
)
define
(
`
intra_part_mask_ub
', `tmp_reg1.28'
)
define
(
`
mb_intra_struct_ub
', `tmp_reg1.29'
)
define
(
`tmp_reg2', `
r34
'
)
define
(
`tmp_x_w', `
tmp_reg2.0
'
)
define
(
`tmp_reg3', `
r35
'
)
/*
*
__START
*/
__START:
mov
(
16
)
tmp_reg0.0
<
1
>
:
UD
0x0
:
UD
{
al
ign1
}
;
mov
(
16
)
tmp_reg2.0
<
1
>
:
UD
0x0
:
UD
{
al
ign1
}
;
/*
*
Media
Read
Message
--
fetch
neighbor
edge
pixels
*/
/*
ROW
*/
mul
(
2
)
tmp_reg0.0
<
1
>
:
D
orig_xy_ub
<
2
,
2
,
1
>
:
UB
16
:
UW
{
al
ign1
}
; /* (x, y) * 16 */
add
(
1
)
tmp_reg0.0
<
1
>
:
D
tmp_reg0.0
<
0
,
1
,
0
>
:
D
-
8
:
W
{
al
ign1
}
; /* X offset */
add
(
1
)
tmp_reg0.4
<
1
>
:
D
tmp_reg0.4
<
0
,
1
,
0
>
:
D
-
1
:
W
{
al
ign1
}
; /* Y offset */
mov
(
1
)
tmp_reg0.8
<
1
>
:
UD
BL
OCK_32X1
{
al
ign1
}
;
mov
(
1
)
tmp_reg0.20
<
1
>
:
UB
thread_id_ub
{
al
ign1
}
; /* dispatch id */
mov
(
8
)
msg_reg0.0
<
1
>
:
UD
tmp_reg0.0
<
8
,
8
,
1
>
:
UD
{
al
ign1
}
;
send
(
16
)
0
INEP_ROW
null
read
(
BIND_IDX_INEP
,
0
,
0
,
4
)
mlen
1
rlen
1
{
al
ign1
}
;
/*
COL
*/
mul
(
2
)
tmp_reg0.0
<
1
>
:
D
orig_xy_ub
<
2
,
2
,
1
>
:
UB
16
:
UW
{
al
ign1
}
; /* (x, y) * 16 */
add
(
1
)
tmp_reg0.0
<
1
>
:
D
tmp_reg0.0
<
0
,
1
,
0
>
:
D
-
4
:
W
{
al
ign1
}
; /* X offset */
mov
(
1
)
tmp_reg0.8
<
1
>
:
UD
BL
OCK_4X16
{
al
ign1
}
;
mov
(
1
)
tmp_reg0.20
<
1
>
:
UB
thread_id_ub
{
al
ign1
}
; /* dispatch id */
mov
(
8
)
msg_reg0.0
<
1
>
:
UD
tmp_reg0.0
<
8
,
8
,
1
>
:
UD
{
al
ign1
}
;
send
(
16
)
0
INEP_COL0
null
read
(
BIND_IDX_INEP
,
0
,
0
,
4
)
mlen
1
rlen
2
{
al
ign1
}
;
/*
*
VME
message
*/
/*
m0
*/
mul
(
2
)
tmp_reg0.8
<
1
>
:
UW
orig_xy_ub
<
2
,
2
,
1
>
:
UB
16
:
UW
{
al
ign1
}
; /* (x, y) * 16 */
mov
(
1
)
tmp_reg0.20
<
1
>
:
UB
thread_id_ub
{
al
ign1
}
; /* dispatch id */
mov
(
8
)
msg_reg0.0
<
1
>
:
UD
tmp_reg0.0
<
8
,
8
,
1
>
:
UD
{
al
ign1
}
;
/*
m1
*/
mov
(
1
)
intra_part_mask_ub
<
1
>
:
UB
LUMA_INTRA_8x8_DISABLE
+
LUMA_INTRA_4x4_DISABLE
{
al
ign1
}
;
cmp.nz.f0.0
(
1
)
null
<
1
>
:
UW
orig_x_ub
<
0
,
1
,
0
>
:
UB
0
:
UW
{
al
ign1
}
; /* X != 0 */
(
f0.0
)
add
(
1
)
mb_intra_struct_ub
<
1
>
:
UB
mb_intra_struct_ub
<
0
,
1
,
0
>
:
UB
INTRA_PRED_AVAIL_FLAG_AE
{
al
ign1
}
; /* A */
cmp.nz.f0.0
(
1
)
null
<
1
>
:
UW
orig_y_ub
<
0
,
1
,
0
>
:
UB
0
:
UW
{
al
ign1
}
; /* Y != 0 */
(
f0.0
)
add
(
1
)
mb_intra_struct_ub
<
1
>
:
UB
mb_intra_struct_ub
<
0
,
1
,
0
>
:
UB
INTRA_PRED_AVAIL_FLAG_B
{
al
ign1
}
; /* B */
mul.nz.f0.0
(
1
)
null
<
1
>
:
UW
orig_x_ub
<
0
,
1
,
0
>
:
UB
orig_y_ub
<
0
,
1
,
0
>
:
UB
{
al
ign1
}
; /* X * Y != 0 */
(
f0.0
)
add
(
1
)
mb_intra_struct_ub
<
1
>
:
UB
mb_intra_struct_ub
<
0
,
1
,
0
>
:
UB
INTRA_PRED_AVAIL_FLAG_D
{
al
ign1
}
; /* D */
add
(
1
)
tmp_x_w
<
1
>
:
W
orig_x_ub
<
0
,
1
,
0
>
:
UB
1
:
UW
{
al
ign1
}
; /* X + 1 */
add
(
1
)
tmp_x_w
<
1
>
:
W
w_in_mb_uw
<
0
,
1
,
0
>
:
UW
-
tmp_x_w
<
0
,
1
,
0
>
:
W
{
al
ign1
}
; /* width - (X + 1) */
mul.nz.f0.0
(
1
)
null
<
1
>
:
UD
tmp_x_w
<
0
,
1
,
0
>
:
W
orig_y_ub
<
0
,
1
,
0
>
:
UB
{
al
ign1
}
; /* (width - (X + 1)) * Y != 0 */
(
f0.0
)
add
(
1
)
mb_intra_struct_ub
<
1
>
:
UB
mb_intra_struct_ub
<
0
,
1
,
0
>
:
UB
INTRA_PRED_AVAIL_FLAG_C
{
al
ign1
}
; /* C */
mov
(
8
)
msg_reg1
<
1
>
:
UD
tmp_reg1.0
<
8
,
8
,
1
>
:
UD
{
al
ign1
}
;
/*
m2
*/
mov
(
8
)
msg_reg2
<
1
>
:
UD
INEP_ROW.0
<
8
,
8
,
1
>
:
UD
{
al
ign1
}
;
/*
m3
*/
mov
(
8
)
msg_reg3
<
1
>
:
UD
0x0
{
al
ign1
}
;
mov
(
16
)
msg_reg3.0
<
1
>
:
UB
INEP_COL0.3
<
32
,
8
,
4
>
:
UB
{
al
ign1
}
;
mov
(
1
)
msg_reg3.16
<
1
>
:
UD
INTRA_PREDICTORE_MODE
{
al
ign1
}
;
send
(
8
)
0
vme_wb
null
vme
(
BIND_IDX_VME
,
0
,
0
,
2
)
mlen
4
rlen
1
{
al
ign1
}
;
/*
*
Oword
Bl
ock
Write
message
*/
mul
(
1
)
tmp_reg3.8
<
1
>
:
UD
w_in_mb_uw
<
0
,
1
,
0
>
:
UW
orig_y_ub
<
0
,
1
,
0
>
:
UB
{
al
ign1
}
;
add
(
1
)
tmp_reg3.8
<
1
>
:
UD
tmp_reg3.8
<
0
,
1
,
0
>
:
UD
orig_x_ub
<
0
,
1
,
0
>
:
UB
{
al
ign1
}
;
mov
(
1
)
tmp_reg3.20
<
1
>
:
UB
thread_id_ub
{
al
ign1
}
; /* dispatch id */
mov
(
8
)
msg_reg0.0
<
1
>
:
UD
tmp_reg3
<
8
,
8
,
1
>
:
UD
{
al
ign1
}
;
mov
(
1
)
msg_reg1.0
<
1
>
:
UD
vme_wb.0
<
0
,
1
,
0
>
:
UD
{
al
ign1
}
;
mov
(
1
)
msg_reg1.4
<
1
>
:
UD
vme_wb.16
<
0
,
1
,
0
>
:
UD
{
al
ign1
}
;
mov
(
1
)
msg_reg1.8
<
1
>
:
UD
vme_wb.20
<
0
,
1
,
0
>
:
UD
{
al
ign1
}
;
mov
(
1
)
msg_reg1.12
<
1
>
:
UD
vme_wb.24
<
0
,
1
,
0
>
:
UD
{
al
ign1
}
;
/*
bind
index
3
,
write
1
oword
,
msg
type
:
8
(
OWord
Bl
ock
Write
)
*/
/*
bind
index
3
,
write
1
oword
,
msg
type
:
8
(
OWord
Bl
ock
Write
)
*/
send
(
16
)
0
r13
null
write
(
3
,
0
,
8
,
1
)
mlen
2
rlen
1
{
al
ign1
}
;
send
(
16
)
0
obw_wb
null
write
(
BIND_IDX_OUTPUT
,
0
,
8
,
1
)
mlen
2
rlen
1
{
al
ign1
}
;
mov
(
8
)
m0.0
<
1
>
:
UD
r0
<
8
,
8
,
1
>
:
UD
{
al
ign1
}
;
/*
*
kill
thread
*/
mov
(
8
)
msg_reg0
<
1
>
:
UD
r0
<
8
,
8
,
1
>
:
UD
{
al
ign1
}
;
send
(
16
)
0
acc0
<
1
>
UW
null
thread_spawner
(
0
,
0
,
1
)
mlen
1
rlen
0
{
al
ign1
EOT
}
;
send
(
16
)
0
acc0
<
1
>
UW
null
thread_spawner
(
0
,
0
,
1
)
mlen
1
rlen
0
{
al
ign1
EOT
}
;
i965_drv_video/shaders/vme/intra_frame.g6b
View file @
85e330ce
{ 0x00000001, 0x20b40231, 0x00200014, 0x00000000 },
{ 0x00800001, 0x24000061, 0x00000000, 0x00000000 },
{ 0x00600001, 0x20000022, 0x008d00a0, 0x00000000 },
{ 0x00800001, 0x24400061, 0x00000000, 0x00000000 },
{ 0x00600001, 0x20200022, 0x008d00c0, 0x00000000 },
{ 0x00200041, 0x24002e25, 0x004500a0, 0x00100010 },
{ 0x00600001, 0x20400022, 0x008d00e0, 0x00000000 },
{ 0x00000040, 0x24003ca5, 0x00000400, 0xfff8fff8 },
{ 0x00600001, 0x20600022, 0x008d0100, 0x00000000 },
{ 0x00000040, 0x24043ca5, 0x00000404, 0xffffffff },
{ 0x00000001, 0x240800e1, 0x00000000, 0x0000001f },
{ 0x00000001, 0x24140231, 0x00000014, 0x00000000 },
{ 0x00600001, 0x20000022, 0x008d0400, 0x00000000 },
{ 0x05800031, 0x21c01cdd, 0x00000000, 0x02188004 },
{ 0x00200041, 0x24002e25, 0x004500a0, 0x00100010 },
{ 0x00000040, 0x24003ca5, 0x00000400, 0xfffcfffc },
{ 0x00000001, 0x240800e1, 0x00000000, 0x000f0003 },
{ 0x00000001, 0x24140231, 0x00000014, 0x00000000 },
{ 0x00600001, 0x20000022, 0x008d0400, 0x00000000 },
{ 0x05800031, 0x22001cdd, 0x00000000, 0x02288004 },
{ 0x00200041, 0x24082e29, 0x004500a0, 0x00100010 },
{ 0x00000001, 0x24140231, 0x00000014, 0x00000000 },
{ 0x00600001, 0x20000022, 0x008d0400, 0x00000000 },
{ 0x00000001, 0x243c00f1, 0x00000000, 0x00000006 },
{ 0x02000010, 0x20002e28, 0x000000a0, 0x00000000 },
{ 0x00010040, 0x243d1e31, 0x0000043d, 0x00000060 },
{ 0x02000010, 0x20002e28, 0x000000a1, 0x00000000 },
{ 0x00010040, 0x243d1e31, 0x0000043d, 0x00000010 },
{ 0x02000041, 0x20004628, 0x000000a0, 0x000000a1 },
{ 0x00010040, 0x243d1e31, 0x0000043d, 0x00000004 },
{ 0x00000040, 0x24402e2d, 0x000000a0, 0x00010001 },
{ 0x00000040, 0x2440352d, 0x000000a2, 0x00004440 },
{ 0x02000041, 0x200045a0, 0x00000440, 0x000000a1 },
{ 0x00010040, 0x243d1e31, 0x0000043d, 0x00000008 },
{ 0x00600001, 0x20200022, 0x008d0420, 0x00000000 },
{ 0x00600001, 0x20400022, 0x008d01c0, 0x00000000 },
{ 0x00600001, 0x206000e2, 0x00000000, 0x00000000 },
{ 0x00800001, 0x20600232, 0x00cf0203, 0x00000000 },
{ 0x00000001, 0x20700062, 0x00000000, 0x11111111 },
{ 0x08600031, 0x21801cdd, 0x00000000, 0x08184000 },
{ 0x08600031, 0x21801cdd, 0x00000000, 0x08184000 },
{ 0x00000001, 0x21340231, 0x00200014, 0x00000000 },
{ 0x00000041, 0x24684521, 0x000000a2, 0x000000a1 },
{ 0x00600001, 0x20000022, 0x008d0120, 0x00000000 },
{ 0x00000040, 0x24684421, 0x00000468, 0x000000a0 },
{ 0x00000001, 0x24740231, 0x00000014, 0x00000000 },
{ 0x00600001, 0x20000022, 0x008d0460, 0x00000000 },
{ 0x00000001, 0x20200022, 0x00000180, 0x00000000 },
{ 0x00000001, 0x20200022, 0x00000180, 0x00000000 },
{ 0x00000001, 0x20240022, 0x00000190, 0x00000000 },
{ 0x00000001, 0x20240022, 0x00000190, 0x00000000 },
{ 0x00000001, 0x20280022, 0x00000194, 0x00000000 },
{ 0x00000001, 0x20280022, 0x00000194, 0x00000000 },
...
...
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