i965_drv_video: encode on Ivybridge

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>

i965_drv_video/i965_defines.h

@@ -283,6 +283,7 @@
 #define MFX_AES_STATE                           MFX(2, 0, 0, 5)
 #define MFX_STATE_POINTER                       MFX(2, 0, 0, 6)
 #define MFX_QM_STATE                            MFX(2, 0, 0, 7)
+#define MFX_FQM_STATE                           MFX(2, 0, 0, 8)
 
 #define MFX_WAIT                                MFX(1, 0, 0, 0)
 

i965_drv_video/i965_drv_video.c

@@ -158,7 +158,7 @@ static struct hw_codec_info gen6_hw_codec_info = {
 extern struct hw_context *gen7_dec_hw_context_init(VADriverContextP, VAProfile);
 static struct hw_codec_info gen7_hw_codec_info = {
     .dec_hw_context_init = gen7_dec_hw_context_init,
-    .enc_hw_context_init = NULL,
+    .enc_hw_context_init = gen6_enc_hw_context_init,
 };
 
 VAStatus 

i965_drv_video/i965_structs.h

@@ -1252,4 +1252,56 @@ struct gen7_sampler_state
    } ss3;
 };
 
+struct gen7_surface_state2
+{
+    struct {
+        unsigned int surface_base_address;
+    } ss0;
+
+    struct {
+        unsigned int cbcr_pixel_offset_v_direction:2;
+        unsigned int picture_structure:2;
+        unsigned int width:14;
+        unsigned int height:14;
+    } ss1;
+
+    struct {
+        unsigned int tile_walk:1;
+        unsigned int tiled_surface:1;
+        unsigned int half_pitch_for_chroma:1;
+        unsigned int pitch:18;
+        unsigned int pad0:1;
+        unsigned int surface_object_control_data:4;
+        unsigned int pad1:1;
+        unsigned int interleave_chroma:1;
+        unsigned int surface_format:4;
+    } ss2;
+
+    struct {
+        unsigned int y_offset_for_cb:15;
+        unsigned int pad0:1;
+        unsigned int x_offset_for_cb:14;
+        unsigned int pad1:2;
+    } ss3;
+
+    struct {
+        unsigned int y_offset_for_cr:15;
+        unsigned int pad0:1;
+        unsigned int x_offset_for_cr:14;
+        unsigned int pad1:2;
+    } ss4;
+
+    struct {
+        unsigned int pad0;
+    } ss5;
+
+    struct {
+        unsigned int pad0;
+    } ss6;
+
+    struct {
+        unsigned int pad0;
+    } ss7;
+};
+
 #endif /* _I965_STRUCTS_H_ */

i965_drv_video/intel_batchbuffer.c

@@ -166,10 +166,19 @@ intel_batchbuffer_emit_mi_flush(struct intel_batchbuffer *batch)
         if (batch->flag == I915_EXEC_RENDER) {
             BEGIN_BATCH(batch, 4);
             OUT_BATCH(batch, CMD_PIPE_CONTROL | 0x2);
+
+            if (IS_GEN6(intel->device_id))
+                OUT_BATCH(batch, 
+                          CMD_PIPE_CONTROL_WC_FLUSH |
+                          CMD_PIPE_CONTROL_TC_FLUSH |
+                          CMD_PIPE_CONTROL_NOWRITE);
+            else
                 OUT_BATCH(batch, 
                           CMD_PIPE_CONTROL_WC_FLUSH |
                           CMD_PIPE_CONTROL_TC_FLUSH |
+                          CMD_PIPE_CONTROL_DC_FLUSH |
                           CMD_PIPE_CONTROL_NOWRITE);
+
             OUT_BATCH(batch, 0);
             OUT_BATCH(batch, 0);
             ADVANCE_BATCH(batch);

i965_drv_video/intel_driver.h

@@ -50,6 +50,7 @@
 #define CMD_PIPE_CONTROL_IS_FLUSH               (1 << 11)
 #define CMD_PIPE_CONTROL_TC_FLUSH               (1 << 10)
 #define CMD_PIPE_CONTROL_NOTIFY_ENABLE          (1 << 8)
+#define CMD_PIPE_CONTROL_DC_FLUSH               (1 << 5)
 #define CMD_PIPE_CONTROL_GLOBAL_GTT             (1 << 2)
 #define CMD_PIPE_CONTROL_LOCAL_PGTT             (0 << 2)
 #define CMD_PIPE_CONTROL_DEPTH_CACHE_FLUSH      (1 << 0)