i965_drv_video: H.264 & MPEG2 decoding on Ivybridge

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>

i965_drv_video/Makefile.am

@@ -47,7 +47,8 @@ i965_drv_video_la_SOURCES =	\
 	gen6_mfd.c		\
 	i965_encoder.c		\
 	gen6_vme.c		\
-	gen6_mfc.c
+	gen6_mfc.c		\
+	gen7_mfd.c
 
 noinst_HEADERS =                \
 	object_heap.h           \
@@ -71,4 +72,5 @@ noinst_HEADERS =                \
 	gen6_vme.h		\
 	gen6_mfc.h		\
 	intel_compiler.h	\
-	i965_mutext.h
+	i965_mutext.h		\
+	gen7_mfd.h

i965_drv_video/gen7_mfd.h

+/*
+ * Copyright © 2011 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
+ * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
+ * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ *    Xiang Haihao <haihao.xiang@intel.com>
+ *
+ */
+
+#ifndef _GEN7_MFD_H_
+#define _GEN7_MFD_H_
+
+#include <xf86drm.h>
+#include <drm.h>
+#include <i915_drm.h>
+#include <intel_bufmgr.h>
+
+struct gen7_avc_surface
+{
+    dri_bo *dmv_top;
+    dri_bo *dmv_bottom;
+    int dmv_bottom_flag;
+};
+
+#define GEN7_VC1_I_PICTURE              0
+#define GEN7_VC1_P_PICTURE              1
+#define GEN7_VC1_B_PICTURE              2
+#define GEN7_VC1_BI_PICTURE             3
+#define GEN7_VC1_SKIPPED_PICTURE        4
+
+#define GEN7_VC1_SIMPLE_PROFILE         0
+#define GEN7_VC1_MAIN_PROFILE           1
+#define GEN7_VC1_ADVANCED_PROFILE       2
+#define GEN7_VC1_RESERVED_PROFILE       3
+
+struct gen7_vc1_surface
+{
+    dri_bo *dmv;
+    int picture_type;
+};
+
+#define MAX_MFX_REFERENCE_SURFACES        16
+struct hw_context;
+
+struct gen7_mfd_context
+{
+    struct hw_context base;
+
+    struct {
+        VASurfaceID surface_id;
+        int frame_store_id;
+    } reference_surface[MAX_MFX_REFERENCE_SURFACES];
+
+    struct {
+        dri_bo *bo;
+        int valid;
+    } post_deblocking_output;
+
+    struct {
+        dri_bo *bo;
+        int valid;
+    } pre_deblocking_output;
+
+    struct {
+        dri_bo *bo;
+        int valid;
+    } intra_row_store_scratch_buffer;
+
+    struct {
+        dri_bo *bo;
+        int valid;
+    } deblocking_filter_row_store_scratch_buffer;
+
+    struct {
+        dri_bo *bo;
+        int valid;
+    } bsd_mpc_row_store_scratch_buffer;
+
+    struct {
+        dri_bo *bo;
+        int valid;
+    } mpr_row_store_scratch_buffer;
+
+    struct {
+        dri_bo *bo;
+        int valid;
+    } bitplane_read_buffer;
+};
+
+#endif /* _GEN7_MFD_H_ */

i965_drv_video/i965_defines.h

@@ -157,6 +157,7 @@
 #define MFX_BSP_BUF_BASE_ADDR_STATE             MFX(2, 0, 0, 4)
 #define MFX_AES_STATE                           MFX(2, 0, 0, 5)
 #define MFX_STATE_POINTER                       MFX(2, 0, 0, 6)
+#define MFX_QM_STATE                            MFX(2, 0, 0, 7)
 
 #define MFX_WAIT                                MFX(1, 0, 0, 0)
 
@@ -536,10 +537,26 @@
 #define MFX_FORMAT_MPEG2        0
 #define MFX_FORMAT_VC1          1
 #define MFX_FORMAT_AVC          2
+#define MFX_FORMAT_JPEG         3
+
+#define MFX_SHORT_MODE          0
+#define MFX_LONG_MODE           1
 
 #define MFX_CODEC_DECODE        0
 #define MFX_CODEC_ENCODE        1
 
+#define MFX_QM_AVC_4X4_INTRA_MATRIX     0
+#define MFX_QM_AVC_4X4_INTER_MATRIX     1
+#define MFX_QM_AVC_8x8_INTRA_MATRIX     2
+#define MFX_QM_AVC_8x8_INTER_MATRIX     3
+
+#define MFX_QM_MPEG_INTRA_QUANTIZER_MATRIX      0
+#define MFX_QM_MPEG_NON_INTRA_QUANTIZER_MATRIX  1
+
+#define MFX_QM_JPEG_LUMA_Y_QUANTIZER_MATRIX     0
+#define MFX_QM_JPEG_CHROMA_CB_QUANTIZER_MATRIX  1
+#define MFX_QM_JPEG_CHROMA_CR_QUANTIZER_MATRIX  2
+
 #define MFD_MODE_VLD            0
 #define MFD_MODE_IT             1
 

i965_drv_video/i965_drv_video.c

@@ -155,6 +155,12 @@ static struct hw_codec_info gen6_hw_codec_info = {
     .enc_hw_context_init = gen6_enc_hw_context_init,
 };
 
+extern struct hw_context *gen7_dec_hw_context_init(VADriverContextP, VAProfile);
+static struct hw_codec_info gen7_hw_codec_info = {
+    .dec_hw_context_init = gen7_dec_hw_context_init,
+    .enc_hw_context_init = NULL,
+};
+
 VAStatus 
 i965_QueryConfigProfiles(VADriverContextP ctx,
                          VAProfile *profile_list,       /* out */
@@ -1649,7 +1655,7 @@ i965_Init(VADriverContextP ctx)
     else if (IS_GEN6(i965->intel.device_id))
         i965->codec_info = &gen6_hw_codec_info;
     else if (IS_GEN7(i965->intel.device_id))
-        i965->codec_info = &gen6_hw_codec_info;
+        i965->codec_info = &gen7_hw_codec_info;
     else
         return VA_STATUS_ERROR_UNKNOWN;