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Commit 62641bd7 authored by Xiang, Haihao's avatar Xiang, Haihao
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i965_drv_video: deinterlacing & scaling 

Signed-off-by: default avatarXiang, Haihao <haihao.xiang@intel.com>
parent 20975a94
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Showing with 2584 additions and 15 deletions
i965_drv_video/Makefile.am
View file @ 62641bd7
......@@ -42,7 +42,8 @@ i965_drv_video_la_SOURCES = \
i965_drv_video.c \
i965_avc_bsd.c \
i965_avc_hw_scoreboard.c\
i965_avc_ildb.c
i965_avc_ildb.c \
i965_post_processing.c
noinst_HEADERS = \
object_heap.h \
......@@ -59,4 +60,5 @@ noinst_HEADERS = \
i965_structs.h \
i965_avc_bsd.h \
i965_avc_hw_scoreboard.h\
i965_avc_ildb.h
i965_avc_ildb.h \
i965_post_processing.h
i965_drv_video/i965_defines.h
View file @ 62641bd7
......@@ -357,6 +357,29 @@
#define SCOREBOARD_STALLING 0
#define SCOREBOARD_NON_STALLING 1
#define SURFACE_FORMAT_YCRCB_NORMAL 0
#define SURFACE_FORMAT_YCRCB_SWAPUVY 1
#define SURFACE_FORMAT_YCRCB_SWAPUV 2
#define SURFACE_FORMAT_YCRCB_SWAPY 3
#define SURFACE_FORMAT_PLANAR_420_8 4
#define SURFACE_FORMAT_PLANAR_411_8 5
#define SURFACE_FORMAT_PLANAR_422_8 6
#define SURFACE_FORMAT_STMM_DN_STATISTICS 7
#define SURFACE_FORMAT_R10G10B10A2_UNORM 8
#define SURFACE_FORMAT_R8G8B8A8_UNORM 9
#define SURFACE_FORMAT_R8B8_UNORM 10
#define SURFACE_FORMAT_R8_UNORM 11
#define SURFACE_FORMAT_Y8_UNORM 12
#define AVS_FILTER_ADAPTIVE_8_TAP 0
#define AVS_FILTER_NEAREST 1
#define IEF_FILTER_COMBO 0
#define IEF_FILTER_DETAIL 1
#define IEF_FILTER_SIZE_3X3 0
#define IEF_FILTER_SIZE_5X5 1
#define URB_SIZE(intel) (IS_IRONLAKE(intel->device_id) ? 1024 : \
IS_G4X(intel->device_id) ? 384 : 256)
#endif /* _I965_DEFINES_H_ */
i965_drv_video/i965_drv_video.c
View file @ 62641bd7
......@@ -350,6 +350,8 @@ i965_destroy_surface(struct object_heap *heap, struct object_base *obj)
dri_bo_unreference(obj_surface->bo);
obj_surface->bo = NULL;
dri_bo_unreference(obj_surface->pp_out_bo);
obj_surface->pp_out_bo = NULL;
if (obj_surface->free_private_data != NULL) {
obj_surface->free_private_data(&obj_surface->private_data);
......@@ -395,6 +397,7 @@ i965_CreateSurfaces(VADriverContextP ctx,
obj_surface->size = SIZE_YUV420(obj_surface->width, obj_surface->height);
obj_surface->flags = SURFACE_REFERENCED;
obj_surface->bo = NULL;
obj_surface->pp_out_bo = NULL;
obj_surface->private_data = NULL;
obj_surface->free_private_data = NULL;
}
......@@ -1644,7 +1647,7 @@ i965_GetImage(VADriverContextP ctx,
VAStatus
i965_PutSurface(VADriverContextP ctx,
VASurfaceID surface,
Drawable draw, /* X Drawable */
void *draw, /* X Drawable */
short srcx,
short srcy,
unsigned short srcw,
......@@ -1667,6 +1670,7 @@ i965_PutSurface(VADriverContextP ctx,
int ret;
uint32_t name;
Bool new_region = False;
int pp_flag = 0;
/* Currently don't support DRI1 */
if (dri_state->driConnectedFlag != VA_DRI2)
return VA_STATUS_ERROR_UNKNOWN;
......@@ -1678,7 +1682,7 @@ i965_PutSurface(VADriverContextP ctx,
if (obj_surface->bo == NULL)
return VA_STATUS_SUCCESS;
dri_drawable = dri_get_drawable(ctx, draw);
dri_drawable = dri_get_drawable(ctx, (Drawable)draw);
assert(dri_drawable);
buffer = dri_get_rendering_buffer(ctx, dri_drawable);
......@@ -1716,9 +1720,16 @@ i965_PutSurface(VADriverContextP ctx,
assert(ret == 0);
}
if ((flags & VA_FILTER_SCALING_MASK) == VA_FILTER_SCALING_NL_ANAMORPHIC)
pp_flag |= I965_PP_FLAG_AVS;
if (flags & (VA_BOTTOM_FIELD | VA_TOP_FIELD))
pp_flag |= I965_PP_FLAG_DEINTERLACING;
i965_render_put_surface(ctx, surface,
srcx, srcy, srcw, srch,
destx, desty, destw, desth);
destx, desty, destw, desth,
pp_flag);
if(obj_surface->subpic != VA_INVALID_ID) {
i965_render_put_subpic(ctx, surface,
......
i965_drv_video/i965_drv_video.h
View file @ 62641bd7
......@@ -109,6 +109,11 @@ struct object_surface
int orig_height;
int flags;
dri_bo *bo;
int pp_out_width;
int pp_out_height;
int orig_pp_out_width;
int orig_pp_out_height;
dri_bo *pp_out_bo;
void (*free_private_data)(void **data);
void *private_data;
};
......
i965_drv_video/i965_post_processing.c 0 → 100644
View file @ 62641bd7
This diff is collapsed.
i965_drv_video/i965_post_processing.h 0 → 100644
View file @ 62641bd7
/*
* Copyright © 2010 Intel Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sub license, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial portions
* of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
* IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
* ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* Authors:
* Xiang Haihao <haihao.xiang@intel.com>
*
*/
#ifndef __I965_POST_PROCESSING_H__
#define __I965_POST_PROCESSING_H__
#define MAX_PP_SURFACES 32
#define I965_PP_FLAG_DEINTERLACING 1
#define I965_PP_FLAG_AVS 2
enum
{
PP_NULL = 0,
PP_NV12_LOAD_SAVE,
PP_NV12_SCALING,
PP_NV12_AVS,
PP_NV12_DNDI,
};
struct pp_load_save_context
{
int dest_w;
int dest_h;
};
struct pp_scaling_context
{
int dest_w;
int dest_h;
};
struct pp_avs_context
{
int dest_w;
int dest_h;
int src_w;
int src_h;
};
struct pp_dndi_context
{
int dest_w;
int dest_h;
};
struct i965_post_processing_context
{
int current_pp;
struct {
dri_bo *bo;
} curbe;
struct {
dri_bo *ss_bo;
dri_bo *s_bo;
} surfaces[MAX_PP_SURFACES];
struct {
dri_bo *bo;
} binding_table;
struct {
dri_bo *bo;
} idrt;
struct {
dri_bo *bo;
} vfe_state;
struct {
dri_bo *bo;
dri_bo *bo_8x8;
dri_bo *bo_8x8_uv;
} sampler_state_table;
struct {
unsigned int size;
unsigned int vfe_start;
unsigned int cs_start;
unsigned int num_vfe_entries;
unsigned int num_cs_entries;
unsigned int size_vfe_entry;
unsigned int size_cs_entry;
} urb;
struct {
dri_bo *bo;
} stmm;
union {
struct pp_load_save_context pp_load_save_context;
struct pp_scaling_context pp_scaling_context;
struct pp_avs_context pp_avs_context;
struct pp_dndi_context pp_dndi_context;
} private_context;
int (*pp_x_steps)(void *private_context);
int (*pp_y_steps)(void *private_context);
int (*pp_set_block_parameter)(void *private_context, int x, int y);
};
void
i965_post_processing(VADriverContextP ctx,
VASurfaceID surface,
short srcx,
short srcy,
unsigned short srcw,
unsigned short srch,
short destx,
short desty,
unsigned short destw,
unsigned short desth,
unsigned int pp_index);
void
i965_post_processing_once_init(VADriverContextP ctx);
Bool
i965_post_processing_terminate(VADriverContextP ctx);
#endif /* __I965_POST_PROCESSING_H__ */
i965_drv_video/i965_render.c
View file @ 62641bd7
......@@ -655,12 +655,20 @@ i965_render_src_surfaces_state(VADriverContextP ctx,
obj_surface = SURFACE(surface);
assert(obj_surface);
assert(obj_surface->bo);
w = obj_surface->width;
h = obj_surface->height;
rw = obj_surface->orig_width;
rh = obj_surface->orig_height;
region = obj_surface->bo;
if (obj_surface->pp_out_bo) {
w = obj_surface->pp_out_width;
h = obj_surface->pp_out_height;
rw = obj_surface->orig_pp_out_width;
rh = obj_surface->orig_pp_out_height;
region = obj_surface->pp_out_bo;
} else {
w = obj_surface->width;
h = obj_surface->height;
rw = obj_surface->orig_width;
rh = obj_surface->orig_height;
region = obj_surface->bo;
}
i965_render_src_surface_state(ctx, 1, region, 0, rw, rh, w, I965_SURFACEFORMAT_R8_UNORM); /* Y */
i965_render_src_surface_state(ctx, 2, region, 0, rw, rh, w, I965_SURFACEFORMAT_R8_UNORM);
......@@ -1454,8 +1462,14 @@ i965_render_put_surface(VADriverContextP ctx,
short destx,
short desty,
unsigned short destw,
unsigned short desth)
unsigned short desth,
unsigned int flag)
{
i965_post_processing(ctx, surface,
srcx, srcy, srcw, srch,
destx, desty, destw, desth,
flag);
i965_render_initialize(ctx);
i965_surface_render_state_setup(ctx, surface,
srcx, srcy, srcw, srch,
......@@ -1523,6 +1537,8 @@ i965_render_init(VADriverContextP ctx)
assert(render_state->curbe.bo);
render_state->curbe.upload = 0;
i965_post_processing_once_init(ctx);
return True;
}
......@@ -1533,6 +1549,8 @@ i965_render_terminate(VADriverContextP ctx)
struct i965_driver_data *i965 = i965_driver_data(ctx);
struct i965_render_state *render_state = &i965->render_state;
i965_post_processing_terminate(ctx);
dri_bo_unreference(render_state->curbe.bo);
render_state->curbe.bo = NULL;
......
i965_drv_video/i965_render.h
View file @ 62641bd7
......@@ -31,6 +31,8 @@
#define MAX_RENDER_SURFACES 16
#define MAX_SAMPLERS 16
#include "i965_post_processing.h"
struct i965_render_state
{
struct {
......@@ -65,6 +67,9 @@ struct i965_render_state
int interleaved_uv;
struct intel_region *draw_region;
int pp_flag; /* 0: disable, 1: enable */
struct i965_post_processing_context pp_context;
};
Bool i965_render_init(VADriverContextP ctx);
......@@ -78,7 +83,8 @@ void i965_render_put_surface(VADriverContextP ctx,
short destx,
short desty,
unsigned short destw,
unsigned short desth);
unsigned short desth,
unsigned int flag);
void
......
i965_drv_video/i965_structs.h
View file @ 62641bd7
......@@ -639,4 +639,329 @@ struct i965_cc_unit_state
} cc7;
};
struct i965_sampler_8x8
{
struct {
unsigned int pad0:16;
unsigned int chroma_key_index:2;
unsigned int chroma_key_enable:1;
unsigned int pad1:8;
unsigned int ief_filter_size:1;
unsigned int ief_filter_type:1;
unsigned int ief_bypass:1;
unsigned int pad2:1;
unsigned int avs_filter_type:1;
} dw0;
struct {
unsigned int pad0:5;
unsigned int sampler_8x8_state_pointer:27;
} dw1;
struct {
unsigned int weak_edge_threshold:4;
unsigned int strong_edge_threshold:4;
unsigned int global_noise_estimation:8;
unsigned int pad0:16;
} dw2;
struct {
unsigned int r3x_coefficient:5;
unsigned int pad0:1;
unsigned int r3c_coefficient:5;
unsigned int pad1:3;
unsigned int gain_factor:6;
unsigned int non_edge_weight:3;
unsigned int pad2:1;
unsigned int regular_weight:3;
unsigned int pad3:1;
unsigned int strong_edge_weight:3;
unsigned int pad4:1;
} dw3;
struct {
unsigned int pad0:2;
unsigned int mr_boost:1;
unsigned int mr_threshold:4;
unsigned int steepness_boost:1;
unsigned int steepness_threshold:4;
unsigned int pad1:2;
unsigned int r5x_coefficient:5;
unsigned int pad2:1;
unsigned int r5cx_coefficient:5;
unsigned int pad3:1;
unsigned int r5c_coefficient:5;
unsigned int pad4:1;
} dw4;
struct {
unsigned int pwl1_point_1:8;
unsigned int pwl1_point_2:8;
unsigned int pwl1_point_3:8;
unsigned int pwl1_point_4:8;
} dw5;
struct {
unsigned int pwl1_point_5:8;
unsigned int pwl1_point_6:8;
unsigned int pwl1_r3_bias_0:8;
unsigned int pwl1_r3_bias_1:8;
} dw6;
struct {
unsigned int pwl1_r3_bias_2:8;
unsigned int pwl1_r3_bias_3:8;
unsigned int pwl1_r3_bias_4:8;
unsigned int pwl1_r3_bias_5:8;
} dw7;
struct {
unsigned int pwl1_r3_bias_6:8;
unsigned int pwl1_r5_bias_0:8;
unsigned int pwl1_r5_bias_1:8;
unsigned int pwl1_r5_bias_2:8;
} dw8;
struct {
unsigned int pwl1_r5_bias_3:8;
unsigned int pwl1_r5_bias_4:8;
unsigned int pwl1_r5_bias_5:8;
unsigned int pwl1_r5_bias_6:8;
} dw9;
struct {
int pwl1_r3_slope_0:8;
int pwl1_r3_slope_1:8;
int pwl1_r3_slope_2:8;
int pwl1_r3_slope_3:8;
} dw10;
struct {
int pwl1_r3_slope_4:8;
int pwl1_r3_slope_5:8;
int pwl1_r3_slope_6:8;
int pwl1_r5_slope_0:8;
} dw11;
struct {
int pwl1_r5_slope_1:8;
int pwl1_r5_slope_2:8;
int pwl1_r5_slope_3:8;
int pwl1_r5_slope_4:8;
} dw12;
struct {
int pwl1_r5_slope_5:8;
int pwl1_r5_slope_6:8;
unsigned int limiter_boost:4;
unsigned int pad0:4;
unsigned int minimum_limiter:4;
unsigned int maximum_limiter:4;
} dw13;
struct {
unsigned int pad0:8;
unsigned int clip_limiter:10;
unsigned int pad1:14;
} dw14;
unsigned int dw15; /* Just a pad */
};
struct i965_sampler_8x8_coefficient
{
struct {
int table_0x_filter_c0:8;
int table_0x_filter_c1:8;
int table_0x_filter_c2:8;
int table_0x_filter_c3:8;
} dw0;
struct {
int table_0x_filter_c4:8;
int table_0x_filter_c5:8;
int table_0x_filter_c6:8;
int table_0x_filter_c7:8;
} dw1;
struct {
int table_0y_filter_c0:8;
int table_0y_filter_c1:8;
int table_0y_filter_c2:8;
int table_0y_filter_c3:8;
} dw2;
struct {
int table_0y_filter_c4:8;
int table_0y_filter_c5:8;
int table_0y_filter_c6:8;
int table_0y_filter_c7:8;
} dw3;
struct {
int pad0:16;
int table_1x_filter_c2:8;
int table_1x_filter_c3:8;
} dw4;
struct {
int table_1x_filter_c4:8;
int table_1x_filter_c5:8;
int pad0:16;
} dw5;
struct {
int pad0:16;
int table_1y_filter_c2:8;
int table_1y_filter_c3:8;
} dw6;
struct {
int table_1y_filter_c4:8;
int table_1y_filter_c5:8;
int pad0:16;
} dw7;
};
struct i965_sampler_8x8_state
{
struct i965_sampler_8x8_coefficient coefficients[17];
struct {
unsigned int transition_area_with_8_pixels:3;
unsigned int pad0:1;
unsigned int transition_area_with_4_pixels:3;
unsigned int pad1:1;
unsigned int max_derivative_8_pixels:8;
unsigned int max_derivative_4_pixels:8;
unsigned int default_sharpness_level:8;
} dw136;
struct {
unsigned int bit_field_name:1;
unsigned int adaptive_filter_for_all_channel:1;
unsigned int pad0:19;
unsigned int bypass_y_adaptive_filtering:1;
unsigned int bypass_x_adaptive_filtering:1;
unsigned int pad1:9;
} dw137;
};
struct i965_surface_state2
{
struct {
unsigned int surface_base_address;
} ss0;
struct {
unsigned int cbcr_pixel_offset_v_direction:2;
unsigned int pad0:4;
unsigned int width:13;
unsigned int height:13;
} ss1;
struct {
unsigned int tile_walk:1;
unsigned int tiled_surface:1;
unsigned int half_pitch_for_chroma:1;
unsigned int pitch:17;
unsigned int pad0:2;
unsigned int surface_object_control_data:4;
unsigned int pad1:1;
unsigned int interleave_chroma:1;
unsigned int surface_format:4;
} ss2;
struct {
unsigned int y_offset_for_cb:13;
unsigned int pad0:3;
unsigned int x_offset_for_cb:13;
unsigned int pad1:3;
} ss3;
struct {
unsigned int y_offset_for_cr:13;
unsigned int pad0:3;
unsigned int x_offset_for_cr:13;
unsigned int pad1:3;
} ss4;
};
struct i965_sampler_dndi
{
struct {
unsigned int denoise_asd_threshold:8;
unsigned int denoise_history_delta:8;
unsigned int denoise_maximum_history:8;
unsigned int denoise_stad_threshold:8;
} dw0;
struct {
unsigned int denoise_threshold_for_sum_of_complexity_measure:8;
unsigned int denoise_moving_pixel_threshold:5;
unsigned int stmm_c2:3;
unsigned int low_temporal_difference_threshold:6;
unsigned int pad0:2;
unsigned int temporal_difference_threshold:6;
unsigned int pad1:2;
} dw1;
struct {
unsigned int block_noise_estimate_noise_threshold:8;
unsigned int block_noise_estimate_edge_threshold:8;
unsigned int denoise_edge_threshold:8;
unsigned int good_neighbor_threshold:8;
} dw2;
struct {
unsigned int maximum_stmm:8;
unsigned int multipler_for_vecm:6;
unsigned int pad0:2;
unsigned int blending_constant_across_time_for_small_values_of_stmm:8;
unsigned int blending_constant_across_time_for_large_values_of_stmm:7;
unsigned int stmm_blending_constant_select:1;
} dw3;
struct {
unsigned int sdi_delta:8;
unsigned int sdi_threshold:8;
unsigned int stmm_output_shift:4;
unsigned int stmm_shift_up:2;
unsigned int stmm_shift_down:2;
unsigned int minimum_stmm:8;
} dw4;
struct {
unsigned int fmd_temporal_difference_threshold:8;
unsigned int sdi_fallback_mode_2_constant:8;
unsigned int sdi_fallback_mode_1_t2_constant:8;
unsigned int sdi_fallback_mode_1_t1_constant:8;
} dw5;
struct {
unsigned int dn_enable:1;
unsigned int di_enable:1;
unsigned int di_partial:1;
unsigned int dndi_top_first:1;
unsigned int dndi_stream_id:1;
unsigned int dndi_first_frame:1;
unsigned int progressive_dn:1;
unsigned int pad0:1;
unsigned int fmd_tear_threshold:6;
unsigned int pad1:2;
unsigned int fmd2_vertical_difference_threshold:8;
unsigned int fmd1_vertical_difference_threshold:8;
} dw6;
struct {
unsigned int pad0:8;
unsigned int fmd_for_1st_field_of_current_frame:2;
unsigned int pad1:6;
unsigned int fmd_for_2nd_field_of_previous_frame:2;
unsigned int vdi_walker_enable:1;
unsigned int pad2:4;
unsigned int column_width_minus1:9;
} dw7;
};
#endif /* _I965_STRUCTS_H_ */
i965_drv_video/intel_batchbuffer.c
View file @ 62641bd7
......@@ -37,7 +37,7 @@ static void
intel_batchbuffer_reset(struct intel_batchbuffer *batch)
{
struct intel_driver_data *intel = batch->intel;
int batch_size = batch->flag == I915_EXEC_RENDER ? BATCH_SIZE : (BATCH_SIZE * 8);
int batch_size = BATCH_SIZE;
assert(batch->flag == I915_EXEC_RENDER ||
batch->flag == I915_EXEC_BSD);
......
i965_drv_video/intel_driver.h
View file @ 62641bd7
......@@ -17,7 +17,7 @@
#define INLINE
#endif
#define BATCH_SIZE 0x10000
#define BATCH_SIZE 0x80000
#define BATCH_RESERVED 0x10
#define CMD_MI (0x0 << 29)
......
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