Merge branch 'snb-encoder'

configure.ac

@@ -178,6 +178,7 @@ AC_OUTPUT([
 	i965_drv_video/shaders/mpeg2/vld/Makefile
 	i965_drv_video/shaders/render/Makefile
 	i965_drv_video/shaders/post_processing/Makefile
+	i965_drv_video/shaders/vme/Makefile
 	test/Makefile
 	test/basic/Makefile
 	test/decode/Makefile

i965_drv_video/Makefile.am

@@ -44,7 +44,10 @@ i965_drv_video_la_SOURCES =	\
 	i965_avc_hw_scoreboard.c\
 	i965_avc_ildb.c		\
 	i965_post_processing.c	\
-	gen6_mfd.c
+	gen6_mfd.c		\
+	i965_encoder.c		\
+	gen6_vme.c		\
+	gen6_mfc.c
 
 noinst_HEADERS =                \
 	object_heap.h           \
@@ -63,4 +66,7 @@ noinst_HEADERS =                \
 	i965_avc_hw_scoreboard.h\
 	i965_avc_ildb.h		\
 	i965_post_processing.h	\
-	gen6_mfd.h
+	gen6_mfd.h		\
+	i965_encoder.h		\
+	gen6_vme.h		\
+	gen6_mfc.h

i965_drv_video/gen6_mfc.h

+/*
+ * Copyright © 2010 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
+ * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
+ * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ *    Zhou Chang <chang.zhou@intel.com>
+ *
+ */
+
+#ifndef _GEN6_MFC_BCS_H_
+#define _GEN6_MFC_BCS_H_
+
+#include <xf86drm.h>
+#include <drm.h>
+#include <i915_drm.h>
+#include <intel_bufmgr.h>
+
+struct mfc_encode_state;
+
+#define MAX_MFC_REFERENCE_SURFACES        16
+#define NUM_MFC_DMV_BUFFERS				  34
+struct gen6_mfc_bcs_state 
+{
+    struct {
+        unsigned int width;
+        unsigned int height;
+        unsigned int w_pitch;
+        unsigned int h_pitch;
+    } surface_state;
+
+
+    //MFX_PIPE_BUF_ADDR_STATE
+    struct {
+        dri_bo *bo;                            	
+    } post_deblocking_output;                   		//OUTPUT: reconstructed picture                           
+    
+    struct {  
+        dri_bo *bo;							   	
+    } pre_deblocking_output;                    		//OUTPUT: reconstructed picture with deblocked                           
+
+    struct {
+        dri_bo *bo;
+    } uncompressed_picture_source;						//INPUT: original compressed image
+
+    struct {
+        dri_bo *bo;							  	
+    } intra_row_store_scratch_buffer;					//INTERNAL:
+
+    struct {
+        dri_bo *bo;								
+    } deblocking_filter_row_store_scratch_buffer;		//INTERNAL:
+
+    struct {                                    
+       dri_bo *bo; 
+    } reference_surfaces[MAX_MFC_REFERENCE_SURFACES];	//INTERNAL: refrence surfaces
+
+    //MFX_IND_OBJ_BASE_ADDR_STATE
+    struct{
+        dri_bo *bo;
+    } mfc_indirect_mv_object;							//INPUT: the blocks' mv info
+
+    struct {
+        dri_bo *bo;
+        int offset;
+    } mfc_indirect_pak_bse_object;						//OUTPUT: the compressed bitstream 
+
+    //MFX_BSP_BUF_BASE_ADDR_STATE
+    struct {
+        dri_bo *bo;
+    }bsd_mpc_row_store_scratch_buffer;					//INTERNAL:
+	
+    //MFX_AVC_DIRECTMODE_STATE
+    struct {
+        dri_bo *bo;
+    }direct_mv_buffers[NUM_MFC_DMV_BUFFERS];				//INTERNAL:	0-31 as input,32 and 33 as output
+};
+
+VAStatus gen6_mfc_pipeline(VADriverContextP ctx, 
+                           VAContextID context,                              
+                           struct mfc_encode_state *encode_state);
+
+#endif	/* _GEN6_MFC_BCS_H_ */

i965_drv_video/gen6_vme.h

+/*
+ * Copyright © 2009 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
+ * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
+ * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWAR
+ *
+ * Authors:
+ *    Zhou Chang <chang.zhou@intel.com>
+ *
+ */
+
+#ifndef _GEN6_MEDIA_H_
+#define _GEN6_MEDIA_H_
+
+#include <xf86drm.h>
+#include <drm.h>
+#include <i915_drm.h>
+#include <intel_bufmgr.h>
+
+
+#define MAX_INTERFACE_DESC_GEN6      32
+#define MAX_MEDIA_SURFACES_GEN6      34
+
+struct mfc_encode_state;
+
+struct gen6_media_state 
+{
+    struct {
+        dri_bo *bo;
+    } surface_state[MAX_MEDIA_SURFACES_GEN6];
+
+    struct {
+        dri_bo *bo;
+    } binding_table;
+
+    struct {
+        dri_bo *bo;
+    } idrt;  /* interface descriptor remap table */
+
+    struct {
+        dri_bo *bo;
+    } curbe;
+
+    struct {
+        unsigned int gpgpu_mode:1;
+        unsigned int max_num_threads:16;
+        unsigned int num_urb_entries:8;
+        unsigned int urb_entry_size:16;
+        unsigned int curbe_allocation_size:16;
+    } vfe_state;
+
+    struct {
+        dri_bo *bo;
+    } vme_state;
+
+    struct {
+        dri_bo *bo;
+        unsigned int num_blocks;
+        unsigned int size_block; /* in bytes */
+        unsigned int pitch;
+    } vme_output;
+};
+
+VAStatus gen6_vme_media_pipeline(VADriverContextP ctx,
+                                 VAContextID context,                              
+                                 struct mfc_encode_state *encode_state);
+Bool gen6_vme_init(VADriverContextP ctx);
+Bool gen6_vme_terminate(VADriverContextP ctx);
+
+#endif /* _GEN6_MEDIA_H_ */

i965_drv_video/i965_defines.h

@@ -17,6 +17,9 @@
 #define CMD_SAMPLER_PALETTE_LOAD                CMD(3, 1, 2)
 
 #define CMD_MEDIA_STATE_POINTERS                CMD(2, 0, 0)
+#define CMD_MEDIA_VFE_STATE                     CMD(2, 0, 0)
+#define CMD_MEDIA_CURBE_LOAD                    CMD(2, 0, 1)
+#define CMD_MEDIA_INTERFACE_LOAD                CMD(2, 0, 2)
 #define CMD_MEDIA_OBJECT                        CMD(2, 1, 0)
 #define CMD_MEDIA_OBJECT_EX                     CMD(2, 1, 1)
 
@@ -54,6 +57,8 @@
 /* DW1 */
 # define CMD_CLEAR_PARAMS_DEPTH_CLEAR_VALID     (1 << 15)
 
+#define CMD_PIPE_CONTROL                        CMD(3, 2, 0)
+
 /* for GEN6+ */
 #define GEN6_3DSTATE_SAMPLER_STATE_POINTERS	CMD(3, 0, 0x02)
 # define GEN6_3DSTATE_SAMPLER_STATE_MODIFY_PS	(1 << 12)
@@ -166,6 +171,10 @@
 
 #define MFD_AVC_BSD_OBJECT                      MFX(2, 1, 1, 8)
 
+#define MFC_AVC_FQM_STATE                       MFX(2, 1, 2, 2)
+#define MFC_AVC_INSERT_OBJECT                   MFX(2, 1, 2, 8)
+#define MFC_AVC_PAK_OBJECT                      MFX(2, 1, 2, 9)
+
 #define MFX_MPEG2_PIC_STATE                     MFX(2, 3, 0, 0)
 #define MFX_MPEG2_QM_STATE                      MFX(2, 3, 0, 1)
 

i965_drv_video/i965_drv_video.h

@@ -40,6 +40,9 @@
 #include "i965_media.h"
 #include "i965_render.h"
 
+#include "gen6_vme.h"
+#include "gen6_mfc.h"
+
 #define I965_MAX_PROFILES                       11
 #define I965_MAX_ENTRYPOINTS                    5
 #define I965_MAX_CONFIG_ATTRIBUTES              10
@@ -81,17 +84,32 @@ struct decode_state
     int num_slice_datas;
 };
 
+//keeping mfc encoder's stuff here
+struct mfc_encode_state
+{
+    struct buffer_store *seq_param;
+    struct buffer_store *pic_param;
+    struct buffer_store *pic_control;
+    struct buffer_store *iq_matrix;
+    struct buffer_store *q_matrix;
+    struct buffer_store **slice_params;
+    VASurfaceID current_render_target;
+    int max_slice_params;
+    int num_slice_params;
+};
+
 struct object_context 
 {
     struct object_base base;
     VAContextID context_id;
     VAConfigID config_id;
-    VASurfaceID *render_targets;
+    VASurfaceID *render_targets;		//input->encode, output->decode
     int num_render_targets;
     int picture_width;
     int picture_height;
     int flags;
     struct decode_state decode_state;
+    struct mfc_encode_state encode_state;
 };
 
 #define SURFACE_REFERENCED      (1 << 0)
@@ -168,6 +186,8 @@ struct i965_driver_data
     struct i965_media_state media_state;
     struct i965_render_state render_state;
     void *pp_context;
+    struct gen6_media_state gen6_media_state;
+    struct gen6_mfc_bcs_state gen6_mfc_bcs_state;
 };
 
 #define NEW_CONFIG_ID() object_heap_allocate(&i965->config_heap);

i965_drv_video/i965_encoder.h

+/*
+ * Copyright © 2010 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
+ * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
+ * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ *    Zhou chang <chang.zhou@intel.com>
+ *
+ */
+
+#ifndef _GEN6_MFC_H_
+#define _GEN6_MFC_H_
+
+#include <xf86drm.h>
+#include <drm.h>
+#include <i915_drm.h>
+#include <intel_bufmgr.h>
+#include "i965_structs.h"
+#include "i965_drv_video.h"
+
+
+VAStatus i965_encoder_create_context(
+    VADriverContextP ctx,
+    VAConfigID config_id,
+    int picture_width,
+    int picture_height,
+    int flag,
+    VASurfaceID *render_targets,
+    int num_render_targets,
+    struct object_context *obj_context
+    );
+
+VAStatus i965_encoder_begin_picture(
+    VADriverContextP ctx,
+    VAContextID context,
+    VASurfaceID render_target
+    );
+
+VAStatus i965_encoder_render_picture(VADriverContextP ctx,
+                                 VAContextID context,
+                                 VABufferID *buffers,
+                                 int num_buffers
+    );
+
+VAStatus i965_encoder_end_picture(VADriverContextP ctx, 
+                              VAContextID context
+    );
+
+
+void i965_encoder_destroy_context(struct object_heap *heap, struct object_base *obj);
+
+Bool i965_encoder_init(VADriverContextP ctx);
+Bool i965_encoder_terminate(VADriverContextP ctx);
+
+#endif	/* _GEN6_MFC_H_ */
+
+

i965_drv_video/intel_batchbuffer.c

@@ -431,3 +431,19 @@ intel_batchbuffer_check_batchbuffer_flag(VADriverContextP ctx, int flag)
     intel_batchbuffer_flush_helper(ctx, intel->batch);
     intel->batch->flag = flag;
 }
+
+int
+intel_batchbuffer_check_free_space(VADriverContextP ctx, int size)
+{
+    struct intel_driver_data *intel = intel_driver_data(ctx);
+
+    return intel_batchbuffer_space_helper(intel->batch) >= size;
+}
+
+int
+intel_batchbuffer_check_free_space_bcs(VADriverContextP ctx, int size)
+{
+    struct intel_driver_data *intel = intel_driver_data(ctx);
+
+    return intel_batchbuffer_space_helper(intel->batch_bcs) >= size;
+}

i965_drv_video/intel_batchbuffer.h

@@ -59,6 +59,9 @@ void intel_batchbuffer_advance_batch_bcs(VADriverContextP ctx);
 
 void intel_batchbuffer_check_batchbuffer_flag(VADriverContextP ctx, int flag);
 
+int intel_batchbuffer_check_free_space(VADriverContextP ctx, int size);
+int intel_batchbuffer_check_free_space_bcs(VADriverContextP ctx, int size);
+
 #define __BEGIN_BATCH(ctx, n, flag) do {                        \
         intel_batchbuffer_check_batchbuffer_flag(ctx, flag);    \
         intel_batchbuffer_require_space(ctx, (n) * 4);          \

i965_drv_video/shaders/Makefile.am

-SUBDIRS = h264 mpeg2 render post_processing
+SUBDIRS = h264 mpeg2 render post_processing vme

i965_drv_video/shaders/vme/Makefile.am

+INTEL_G6B = intra_frame.g6b inter_frame.g6b
+INTEL_INC = vme_header.inc
+
+EXTRA_DIST = $(INTEL_G6B)	\
+	$(INTEL_INC)
+
+if HAVE_GEN4ASM
+
+SUFFIXES = .asm .g6b
+.asm.g6b:
+	m4 $*.asm > $*.g6m && intel-gen4asm -g 6 -o $@ $*.g6m && rm $*.g6m
+
+$(INTEL_G6B): $(INTEL_INC)
+
+BUILT_SOURCES= $(INTEL_G6B)
+
+clean-local:
+	-rm -f $(INTEL_G6B)
+
+endif    

i965_drv_video/shaders/vme/inter_frame.asm

+/*
+ * Copyright © <2010>, Intel Corporation.
+ *
+ * This program is licensed under the terms and conditions of the
+ * Eclipse Public License (EPL), version 1.0.  The full text of the EPL is at
+ * http://www.opensource.org/licenses/eclipse-1.0.php.
+ *
+ */
+// Modual name: IntraFrame.asm
+//
+// Make intra predition estimation for Intra frame
+//
+
+//
+//  Now, begin source code....
+//
+
+include(`vme_header.inc')
+
+/*
+ * __START
+ */
+__INTER_START:
+mov  (16) tmp_reg0.0<1>:UD      0x0:UD {align1};
+mov  (16) tmp_reg2.0<1>:UD      0x0:UD {align1};
+
+/*
+ * Media Read Message -- fetch neighbor edge pixels 
+ */
+/* ROW */
+// mul  (2) tmp_reg0.0<1>:D        orig_xy_ub<2,2,1>:UB 16:UW {align1};    /* (x, y) * 16 */
+// add  (1) tmp_reg0.0<1>:D        tmp_reg0.0<0,1,0>:D -8:W {align1};     /* X offset */
+// add  (1) tmp_reg0.4<1>:D        tmp_reg0.4<0,1,0>:D -1:W {align1};     /* Y offset */ 
+// mov  (1) tmp_reg0.8<1>:UD       BLOCK_32X1 {align1};
+// mov  (1) tmp_reg0.20<1>:UB      thread_id_ub {align1};                  /* dispatch id */
+// mov  (8) msg_reg0.0<1>:UD       tmp_reg0.0<8,8,1>:UD {align1};        
+// send (16) 0 INEP_ROW null read(BIND_IDX_INEP, 0, 0, 4) mlen 1 rlen 1 {align1};
+
+/* COL */
+// mul  (2) tmp_reg0.0<1>:D        orig_xy_ub<2,2,1>:UB 16:UW {align1};    /* (x, y) * 16 */
+// add  (1) tmp_reg0.0<1>:D        tmp_reg0.0<0,1,0>:D -4:W {align1};     /* X offset */
+// mov  (1) tmp_reg0.8<1>:UD       BLOCK_4X16 {align1};
+// mov  (1) tmp_reg0.20<1>:UB      thread_id_ub {align1};                  /* dispatch id */
+// mov  (8) msg_reg0.0<1>:UD       tmp_reg0.0<8,8,1>:UD {align1};                
+// send (16) 0 INEP_COL0 null read(BIND_IDX_INEP, 0, 0, 4) mlen 1 rlen 2 {align1};
+
+/*
+ * VME message
+ */
+/* m0 */        
+mul  (2) tmp_reg0.0<1>:UW       orig_xy_ub<2,2,1>:UB 16:UW {align1};    /* (x, y) * 16 */
+mov  (1) tmp_reg0.8<1>:UD       tmp_reg0.0<0,1,0>:UD {align1};
+mov  (1) tmp_reg0.12<1>:UD      INTER_SAD_HAAR + INTRA_SAD_HAAR + SUB_PEL_MODE_QUARTER:UD {align1};    /* 16x16 Source, 1/4 pixel, harr */
+mov  (1) tmp_reg0.20<1>:UB      thread_id_ub {align1};                  /* dispatch id */
+mov  (1) tmp_reg0.22<1>:UW      REF_REGION_SIZE {align1};               /* Reference Width&Height, 32x32 */
+mov  (8) msg_reg0.0<1>:UD       tmp_reg0.0<8,8,1>:UD {align1};
+        
+/* m1 */
+mov  (1) tmp_reg1.4<1>:UD       BI_SUB_MB_PART_MASK + MAX_NUM_MV:UD {align1};                                   /* Default value MAX 32 MVs */
+
+mov  (1) intra_part_mask_ub<1>:UB LUMA_INTRA_8x8_DISABLE + LUMA_INTRA_4x4_DISABLE {align1};
+
+// cmp.nz.f0.0 (1) null<1>:UW orig_x_ub<0,1,0>:UB 0:UW {align1};                                                   /* X != 0 */
+// (f0.0) add (1) mb_intra_struct_ub<1>:UB mb_intra_struct_ub<0,1,0>:UB INTRA_PRED_AVAIL_FLAG_AE {align1};         /* A */
+
+// cmp.nz.f0.0 (1) null<1>:UW orig_y_ub<0,1,0>:UB 0:UW {align1};                                                   /* Y != 0 */
+// (f0.0) add (1) mb_intra_struct_ub<1>:UB mb_intra_struct_ub<0,1,0>:UB INTRA_PRED_AVAIL_FLAG_B {align1};          /* B */
+
+// mul.nz.f0.0 (1) null<1>:UW orig_x_ub<0,1,0>:UB orig_y_ub<0,1,0>:UB {align1};                                    /* X * Y != 0 */
+// (f0.0) add (1) mb_intra_struct_ub<1>:UB mb_intra_struct_ub<0,1,0>:UB INTRA_PRED_AVAIL_FLAG_D {align1};          /* D */
+
+// add  (1) tmp_x_w<1>:W orig_x_ub<0,1,0>:UB 1:UW {align1};                                                        /* X + 1 */
+// add  (1) tmp_x_w<1>:W w_in_mb_uw<0,1,0>:UW -tmp_x_w<0,1,0>:W {align1};                                          /* width - (X + 1) */
+// mul.nz.f0.0 (1) null<1>:UD tmp_x_w<0,1,0>:W orig_y_ub<0,1,0>:UB {align1};                                       /* (width - (X + 1)) * Y != 0 */
+// (f0.0) add (1) mb_intra_struct_ub<1>:UB mb_intra_struct_ub<0,1,0>:UB INTRA_PRED_AVAIL_FLAG_C {align1};          /* C */
+
+mov  (8) msg_reg1<1>:UD         tmp_reg1.0<8,8,1>:UD {align1};
+        
+/* m2 */        
+mov  (8) msg_reg2<1>:UD         INEP_ROW.0<8,8,1>:UD {align1};
+
+/* m3 */        
+mov  (8) msg_reg3<1>:UD         0x0 {align1};
+mov (16) msg_reg3.0<1>:UB       INEP_COL0.3<32,8,4>:UB {align1};
+mov  (1) msg_reg3.16<1>:UD      INTRA_PREDICTORE_MODE {align1};
+
+send (8) 0 vme_wb null vme(BIND_IDX_VME,0,0,VME_MESSAGE_TYPE_INTER) mlen 4 rlen 4 {align1};
+
+/*
+ * Oword Block Write message
+ */
+mul  (1) tmp_reg3.8<1>:UD       w_in_mb_uw<0,1,0>:UW orig_y_ub<0,1,0>:UB {align1};
+add  (1) tmp_reg3.8<1>:UD       tmp_reg3.8<0,1,0>:UD orig_x_ub<0,1,0>:UB {align1};
+mul  (1) tmp_reg3.8<1>:UD       tmp_reg3.8<0,1,0>:UD 0x4:UD {align1};
+mov  (1) tmp_reg3.20<1>:UB      thread_id_ub {align1};                  /* dispatch id */
+mov  (8) msg_reg0.0<1>:UD       tmp_reg3.0<8,8,1>:UD {align1};
+
+mov  (2) tmp_reg3.0<1>:UW       vme_wb1.0<2,2,1>:UB  {align1};
+        
+mov  (8) msg_reg1.0<1>:UD       tmp_reg3.0<0,1,0>:UD   {align1};
+
+mov  (8) msg_reg2.0<1>:UD       tmp_reg3.0<0,1,0>:UD   {align1};
+
+/* bind index 3, write 4 oword, msg type: 8(OWord Block Write) */
+send (16) 0 obw_wb null write(BIND_IDX_OUTPUT, 3, 8, 1) mlen 3 rlen 1 {align1};
+        
+/*
+ * kill thread
+ */        
+mov  (8) msg_reg0<1>:UD         r0<8,8,1>:UD {align1};
+send (16) 0 acc0<1>UW null thread_spawner(0, 0, 1) mlen 1 rlen 0 {align1 EOT};

i965_drv_video/shaders/vme/inter_frame.g6b

+   { 0x00800001, 0x24000061, 0x00000000, 0x00000000 },
+   { 0x00800001, 0x24400061, 0x00000000, 0x00000000 },
+   { 0x00200041, 0x24002e29, 0x004500a0, 0x00100010 },
+   { 0x00000001, 0x24080021, 0x00000400, 0x00000000 },
+   { 0x00000001, 0x240c0061, 0x00000000, 0x00a03000 },
+   { 0x00000001, 0x24140231, 0x00000014, 0x00000000 },
+   { 0x00000001, 0x24160169, 0x00000000, 0x20202020 },
+   { 0x00600001, 0x20000022, 0x008d0400, 0x00000000 },
+   { 0x00000001, 0x24240061, 0x00000000, 0x0c000020 },
+   { 0x00000001, 0x243c00f1, 0x00000000, 0x00000006 },
+   { 0x00600001, 0x20200022, 0x008d0420, 0x00000000 },
+   { 0x00600001, 0x20400022, 0x008d0240, 0x00000000 },
+   { 0x00600001, 0x206000e2, 0x00000000, 0x00000000 },
+   { 0x00800001, 0x20600232, 0x00cf0283, 0x00000000 },
+   { 0x00000001, 0x20700062, 0x00000000, 0x11111111 },
+   { 0x08600031, 0x21801cdd, 0x00000000, 0x08482000 },
+   { 0x00000041, 0x24684521, 0x000000a2, 0x000000a1 },
+   { 0x00000040, 0x24684421, 0x00000468, 0x000000a0 },
+   { 0x00000041, 0x24680c21, 0x00000468, 0x00000004 },
+   { 0x00000001, 0x24740231, 0x00000014, 0x00000000 },
+   { 0x00600001, 0x20000022, 0x008d0460, 0x00000000 },
+   { 0x00200001, 0x24600229, 0x004501a0, 0x00000000 },
+   { 0x00600001, 0x20200022, 0x00000460, 0x00000000 },
+   { 0x00600001, 0x20400022, 0x00000460, 0x00000000 },
+   { 0x05800031, 0x22001cdd, 0x00000000, 0x061b0303 },
+   { 0x00600001, 0x20000022, 0x008d0000, 0x00000000 },
+   { 0x07800031, 0x24001cc8, 0x00000000, 0x82000010 },

i965_drv_video/shaders/vme/intra_frame.asm

+/*
+ * Copyright © <2010>, Intel Corporation.
+ *
+ * This program is licensed under the terms and conditions of the
+ * Eclipse Public License (EPL), version 1.0.  The full text of the EPL is at
+ * http://www.opensource.org/licenses/eclipse-1.0.php.
+ *
+ */
+// Modual name: IntraFrame.asm
+//
+// Make intra predition estimation for Intra frame
+//
+
+//
+//  Now, begin source code....
+//
+
+include(`vme_header.inc')
+
+/*
+ * __START
+ */
+__INTRA_START:
+mov  (16) tmp_reg0.0<1>:UD      0x0:UD {align1};
+mov  (16) tmp_reg2.0<1>:UD      0x0:UD {align1};
+       
+/*
+ * Media Read Message -- fetch neighbor edge pixels 
+ */
+/* ROW */
+mul  (2) tmp_reg0.0<1>:D        orig_xy_ub<2,2,1>:UB 16:UW {align1};    /* (x, y) * 16 */
+add  (1) tmp_reg0.0<1>:D        tmp_reg0.0<0,1,0>:D -8:W {align1};     /* X offset */
+add  (1) tmp_reg0.4<1>:D        tmp_reg0.4<0,1,0>:D -1:W {align1};     /* Y offset */ 
+mov  (1) tmp_reg0.8<1>:UD       BLOCK_32X1 {align1};
+mov  (1) tmp_reg0.20<1>:UB      thread_id_ub {align1};                  /* dispatch id */
+mov  (8) msg_reg0.0<1>:UD       tmp_reg0.0<8,8,1>:UD {align1};        
+send (16) 0 INEP_ROW null read(BIND_IDX_INEP, 0, 0, 4) mlen 1 rlen 1 {align1};
+
+/* COL */
+mul  (2) tmp_reg0.0<1>:D        orig_xy_ub<2,2,1>:UB 16:UW {align1};    /* (x, y) * 16 */
+add  (1) tmp_reg0.0<1>:D        tmp_reg0.0<0,1,0>:D -4:W {align1};     /* X offset */
+mov  (1) tmp_reg0.8<1>:UD       BLOCK_4X16 {align1};
+mov  (1) tmp_reg0.20<1>:UB      thread_id_ub {align1};                  /* dispatch id */
+mov  (8) msg_reg0.0<1>:UD       tmp_reg0.0<8,8,1>:UD {align1};                
+send (16) 0 INEP_COL0 null read(BIND_IDX_INEP, 0, 0, 4) mlen 1 rlen 2 {align1};
+        
+/*
+ * VME message
+ */
+/* m0 */        
+mul  (2) tmp_reg0.8<1>:UW       orig_xy_ub<2,2,1>:UB 16:UW {align1};    /* (x, y) * 16 */
+mov  (1) tmp_reg0.20<1>:UB      thread_id_ub {align1};                  /* dispatch id */
+mov  (8) msg_reg0.0<1>:UD       tmp_reg0.0<8,8,1>:UD {align1};
+
+/* m1 */
+mov  (1) intra_part_mask_ub<1>:UB LUMA_INTRA_8x8_DISABLE + LUMA_INTRA_4x4_DISABLE {align1};
+
+cmp.nz.f0.0 (1) null<1>:UW orig_x_ub<0,1,0>:UB 0:UW {align1};                                                   /* X != 0 */
+(f0.0) add (1) mb_intra_struct_ub<1>:UB mb_intra_struct_ub<0,1,0>:UB INTRA_PRED_AVAIL_FLAG_AE {align1};         /* A */
+
+cmp.nz.f0.0 (1) null<1>:UW orig_y_ub<0,1,0>:UB 0:UW {align1};                                                   /* Y != 0 */
+(f0.0) add (1) mb_intra_struct_ub<1>:UB mb_intra_struct_ub<0,1,0>:UB INTRA_PRED_AVAIL_FLAG_B {align1};          /* B */
+
+mul.nz.f0.0 (1) null<1>:UW orig_x_ub<0,1,0>:UB orig_y_ub<0,1,0>:UB {align1};                                    /* X * Y != 0 */
+(f0.0) add (1) mb_intra_struct_ub<1>:UB mb_intra_struct_ub<0,1,0>:UB INTRA_PRED_AVAIL_FLAG_D {align1};          /* D */
+
+add  (1) tmp_x_w<1>:W orig_x_ub<0,1,0>:UB 1:UW {align1};                                                        /* X + 1 */
+add  (1) tmp_x_w<1>:W w_in_mb_uw<0,1,0>:UW -tmp_x_w<0,1,0>:W {align1};                                          /* width - (X + 1) */
+mul.nz.f0.0 (1) null<1>:UD tmp_x_w<0,1,0>:W orig_y_ub<0,1,0>:UB {align1};                                       /* (width - (X + 1)) * Y != 0 */
+(f0.0) add (1) mb_intra_struct_ub<1>:UB mb_intra_struct_ub<0,1,0>:UB INTRA_PRED_AVAIL_FLAG_C {align1};          /* C */
+
+mov  (8) msg_reg1<1>:UD         tmp_reg1.0<8,8,1>:UD {align1};
+
+/* m2 */        
+mov  (8) msg_reg2<1>:UD         INEP_ROW.0<8,8,1>:UD {align1};
+
+/* m3 */        
+mov  (8) msg_reg3<1>:UD         0x0 {align1};
+mov (16) msg_reg3.0<1>:UB       INEP_COL0.3<32,8,4>:UB {align1};
+mov  (1) msg_reg3.16<1>:UD      INTRA_PREDICTORE_MODE {align1};
+send (8) 0 vme_wb null vme(BIND_IDX_VME,0,0,VME_MESSAGE_TYPE_INTRA) mlen 4 rlen 1 {align1};
+
+/*
+ * Oword Block Write message
+ */
+mul  (1) tmp_reg3.8<1>:UD       w_in_mb_uw<0,1,0>:UW orig_y_ub<0,1,0>:UB {align1};
+add  (1) tmp_reg3.8<1>:UD       tmp_reg3.8<0,1,0>:UD orig_x_ub<0,1,0>:UB {align1};
+mov  (1) tmp_reg3.20<1>:UB      thread_id_ub {align1};                  /* dispatch id */
+mov  (8) msg_reg0.0<1>:UD       tmp_reg3<8,8,1>:UD {align1};
+        
+mov  (1) msg_reg1.0<1>:UD       vme_wb.0<0,1,0>:UD      {align1};
+mov  (1) msg_reg1.4<1>:UD       vme_wb.16<0,1,0>:UD     {align1};
+mov  (1) msg_reg1.8<1>:UD       vme_wb.20<0,1,0>:UD     {align1};
+mov  (1) msg_reg1.12<1>:UD      vme_wb.24<0,1,0>:UD     {align1};
+/* bind index 3, write 1 oword, msg type: 8(OWord Block Write) */
+send (16) 0 obw_wb null write(BIND_IDX_OUTPUT, 0, 8, 1) mlen 2 rlen 1 {align1};
+
+/*
+ * kill thread
+ */        
+mov  (8) msg_reg0<1>:UD         r0<8,8,1>:UD {align1};
+send (16) 0 acc0<1>UW null thread_spawner(0, 0, 1) mlen 1 rlen 0 {align1 EOT};

i965_drv_video/shaders/vme/intra_frame.g6b

+   { 0x00800001, 0x24000061, 0x00000000, 0x00000000 },
+   { 0x00800001, 0x24400061, 0x00000000, 0x00000000 },
+   { 0x00200041, 0x24002e25, 0x004500a0, 0x00100010 },
+   { 0x00000040, 0x24003ca5, 0x00000400, 0xfff8fff8 },
+   { 0x00000040, 0x24043ca5, 0x00000404, 0xffffffff },
+   { 0x00000001, 0x240800e1, 0x00000000, 0x0000001f },
+   { 0x00000001, 0x24140231, 0x00000014, 0x00000000 },
+   { 0x00600001, 0x20000022, 0x008d0400, 0x00000000 },
+   { 0x04800031, 0x22401cdd, 0x00000000, 0x02188004 },
+   { 0x00200041, 0x24002e25, 0x004500a0, 0x00100010 },
+   { 0x00000040, 0x24003ca5, 0x00000400, 0xfffcfffc },
+   { 0x00000001, 0x240800e1, 0x00000000, 0x000f0003 },
+   { 0x00000001, 0x24140231, 0x00000014, 0x00000000 },
+   { 0x00600001, 0x20000022, 0x008d0400, 0x00000000 },
+   { 0x04800031, 0x22801cdd, 0x00000000, 0x02288004 },
+   { 0x00200041, 0x24082e29, 0x004500a0, 0x00100010 },
+   { 0x00000001, 0x24140231, 0x00000014, 0x00000000 },
+   { 0x00600001, 0x20000022, 0x008d0400, 0x00000000 },
+   { 0x00000001, 0x243c00f1, 0x00000000, 0x00000006 },
+   { 0x02000010, 0x20002e28, 0x000000a0, 0x00000000 },
+   { 0x00010040, 0x243d1e31, 0x0000043d, 0x00000060 },
+   { 0x02000010, 0x20002e28, 0x000000a1, 0x00000000 },
+   { 0x00010040, 0x243d1e31, 0x0000043d, 0x00000010 },
+   { 0x02000041, 0x20004628, 0x000000a0, 0x000000a1 },
+   { 0x00010040, 0x243d1e31, 0x0000043d, 0x00000004 },
+   { 0x00000040, 0x24402e2d, 0x000000a0, 0x00010001 },
+   { 0x00000040, 0x2440352d, 0x000000a2, 0x00004440 },
+   { 0x02000041, 0x200045a0, 0x00000440, 0x000000a1 },
+   { 0x00010040, 0x243d1e31, 0x0000043d, 0x00000008 },
+   { 0x00600001, 0x20200022, 0x008d0420, 0x00000000 },
+   { 0x00600001, 0x20400022, 0x008d0240, 0x00000000 },
+   { 0x00600001, 0x206000e2, 0x00000000, 0x00000000 },
+   { 0x00800001, 0x20600232, 0x00cf0283, 0x00000000 },
+   { 0x00000001, 0x20700062, 0x00000000, 0x11111111 },
+   { 0x08600031, 0x21801cdd, 0x00000000, 0x08184000 },
+   { 0x00000041, 0x24684521, 0x000000a2, 0x000000a1 },
+   { 0x00000040, 0x24684421, 0x00000468, 0x000000a0 },
+   { 0x00000001, 0x24740231, 0x00000014, 0x00000000 },
+   { 0x00600001, 0x20000022, 0x008d0460, 0x00000000 },
+   { 0x00000001, 0x20200022, 0x00000180, 0x00000000 },
+   { 0x00000001, 0x20240022, 0x00000190, 0x00000000 },
+   { 0x00000001, 0x20280022, 0x00000194, 0x00000000 },
+   { 0x00000001, 0x202c0022, 0x00000198, 0x00000000 },
+   { 0x05800031, 0x22001cdd, 0x00000000, 0x041b0003 },
+   { 0x00600001, 0x20000022, 0x008d0000, 0x00000000 },
+   { 0x07800031, 0x24001cc8, 0x00000000, 0x82000010 },

i965_drv_video/shaders/vme/vme_header.inc

+/*
+ * Copyright © <2010>, Intel Corporation.
+ *
+ * This program is licensed under the terms and conditions of the
+ * Eclipse Public License (EPL), version 1.0.  The full text of the EPL is at
+ * http://www.opensource.org/licenses/eclipse-1.0.php.
+ *
+ */
+// Modual name: ME_header.inc
+//
+// Global symbols define
+//
+
+/*
+ * Constant
+ */
+define(`VME_MESSAGE_TYPE_INTER',        `1')
+define(`VME_MESSAGE_TYPE_INTRA',        `2')
+define(`VME_MESSAGE_TYPE_MIXED',        `3')
+        
+define(`BLOCK_32X1',                    `0x0000001F')
+define(`BLOCK_4X16',                    `0x000F0003')
+        
+define(`LUMA_INTRA_16x16_DISABLE',      `0x1')
+define(`LUMA_INTRA_8x8_DISABLE',        `0x2')
+define(`LUMA_INTRA_4x4_DISABLE',        `0x4')
+
+define(`INTRA_PRED_AVAIL_FLAG_AE',      `0x60')
+define(`INTRA_PRED_AVAIL_FLAG_B',       `0x10')
+define(`INTRA_PRED_AVAIL_FLAG_C',       `0x8')
+define(`INTRA_PRED_AVAIL_FLAG_D',       `0x4')
+
+define(`BIND_IDX_VME',                  `0')
+define(`BIND_IDX_VME_REF0',             `1')
+define(`BIND_IDX_VME_REF1',             `2')
+define(`BIND_IDX_OUTPUT',               `3')
+define(`BIND_IDX_INEP',                 `4')
+
+define(`SUB_PEL_MODE_INTEGER',          `0x00000000')
+define(`SUB_PEL_MODE_HALF',             `0x00001000')
+define(`SUB_PEL_MODE_QUARTER',          `0x00003000')
+
+define(`INTER_SAD_NONE',                `0x00000000')
+define(`INTER_SAD_HAAR',                `0x00200000')
+
+define(`INTRA_SAD_NONE',                `0x00000000')
+define(`INTRA_SAD_HAAR',                `0x00800000')
+
+define(`REF_REGION_SIZE',               `0x2020:UW')
+
+define(`BI_SUB_MB_PART_MASK',           `0x0c000000')
+define(`MAX_NUM_MV',                    `0x00000020')
+        
+define(`INTRA_PREDICTORE_MODE',         `0x11111111:UD')
+        
+/* GRF registers
+ * r0 header
+ * r1~r4 constant buffer (reserved)
+ * r5 inline data
+ * r6~r11 reserved        
+ * r12 write back of VME message
+ * r13 write back of Oword Block Write        
+ */
+/*
+ * GRF 0 -- header       
+ */        
+define(`thread_id_ub',          `r0.20<0,1,0>:UB')  /* thread id in payload */
+
+/*
+ * GRF 1~4 -- Constant Buffer (reserved)
+ */
+        
+/*
+ * GRF 5 -- inline data
+ */        
+define(`inline_reg0',           `r5')
+define(`w_in_mb_uw',            `inline_reg0.2')
+define(`orig_xy_ub',            `inline_reg0.0')
+define(`orig_x_ub',             `inline_reg0.0')    /* in macroblock */    
+define(`orig_y_ub',             `inline_reg0.1')
+
+/*
+ * GRF 6~11 -- reserved
+ */
+
+/*
+ * GRF 12~15 -- write back for VME message 
+ */
+define(`vme_wb',                `r12')
+define(`vme_wb0',               `r12')
+define(`vme_wb1',               `r13')
+define(`vme_wb2',               `r14')
+define(`vme_wb3',               `r15')
+        
+/*
+ * GRF 16 -- write back for Oword Block Write message with write commit bit
+ */        
+define(`obw_wb',                `r16')
+
+/*
+ * GRF 18~21 -- Intra Neighbor Edge Pixels
+ */
+define(`INEP_ROW',              `r18')
+define(`INEP_COL0',             `r20')
+define(`INEP_COL1',             `r21')
+        
+/*
+ * temporary registers
+ */
+define(`tmp_reg0',              `r32')
+define(`tmp_reg1',              `r33')
+define(`intra_part_mask_ub',    `tmp_reg1.28')        
+define(`mb_intra_struct_ub',    `tmp_reg1.29')
+define(`tmp_reg2',              `r34')
+define(`tmp_x_w',               `tmp_reg2.0')
+define(`tmp_reg3',              `r35')
+
+/*
+ * MRF registers
+ */        
+define(`msg_reg0',              `m0')               /* m0 */
+define(`msg_reg1',              `m1')               /* m1 */
+define(`msg_reg2',              `m2')               /* m2 */
+define(`msg_reg3',              `m3')               /* m3 */
+
+
+
+
+

test/encode/h264encode.c

@@ -461,8 +461,8 @@ int main(int argc,char **argv)
     printf("\n\n");
     
     vaDestroySurfaces(va_dpy,&surface_id[0],SURFACE_NUM);
-    vaDestroyConfig(va_dpy,config_id);
     vaDestroyContext(va_dpy,context_id);
+    vaDestroyConfig(va_dpy,config_id);
     
     vaTerminate(va_dpy);