Merge branch 'i965_h264'

Conflicts:
	va/x11/dri2_util.c

configure.ac

@@ -158,6 +158,8 @@ AC_OUTPUT([
 	dummy_drv_video/Makefile
 	i965_drv_video/Makefile
 	i965_drv_video/shaders/Makefile
+	i965_drv_video/shaders/h264/Makefile
+	i965_drv_video/shaders/h264/mc/Makefile
 	i965_drv_video/shaders/mpeg2/Makefile
 	i965_drv_video/shaders/mpeg2/vld/Makefile
 	i965_drv_video/shaders/render/Makefile

i965_drv_video/Makefile.am

@@ -32,21 +32,31 @@ i965_drv_video_la_LIBADD = ../va/libva-x11.la -lpthread
 i965_drv_video_la_SOURCES =	\
 	object_heap.c		\
 	intel_batchbuffer.c	\
+	intel_batchbuffer_dump.c\
 	intel_memman.c		\
 	intel_driver.c		\
 	i965_media.c		\
 	i965_media_mpeg2.c	\
+	i965_media_h264.c	\
 	i965_render.c		\
-	i965_drv_video.c
+	i965_drv_video.c	\
+	i965_avc_bsd.c		\
+	i965_avc_hw_scoreboard.c\
+	i965_avc_ildb.c
 
 noinst_HEADERS =                \
 	object_heap.h           \
 	intel_batchbuffer.h     \
+	intel_batchbuffer_dump.h\
 	intel_memman.h          \
 	intel_driver.h          \
 	i965_media.h            \
 	i965_media_mpeg2.h      \
+	i965_media_h264.h	\
 	i965_render.h           \
 	i965_drv_video.h        \
 	i965_defines.h          \
-	i965_structs.h
+	i965_structs.h		\
+	i965_avc_bsd.h		\
+	i965_avc_hw_scoreboard.h\
+	i965_avc_ildb.h

i965_drv_video/i965_avc_bsd.h

+/*
+ * Copyright © 2010 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
+ * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
+ * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ *    Xiang Haihao <haihao.xiang@intel.com>
+ *
+ */
+
+#ifndef __I965_AVC_BSD_H__
+#define __I965_AVC_BSD_H__
+
+#define DMV_SIZE        0x88000 /* 557056 bytes for a frame */
+
+struct i965_avc_bsd_context
+{
+    struct {
+        dri_bo *bo;
+    } bsd_raw_store;
+
+    struct {
+        dri_bo *bo;
+    } mpr_row_store;
+
+    int init;
+};
+
+struct i965_avc_bsd_surface
+{
+    struct i965_avc_bsd_context *ctx;
+    dri_bo *dmv_top;
+    dri_bo *dmv_bottom;
+    int dmv_bottom_flag;
+};
+
+void i965_avc_bsd_pipeline(VADriverContextP, struct decode_state *);
+void i965_avc_bsd_decode_init(VADriverContextP);
+Bool i965_avc_bsd_ternimate(struct i965_avc_bsd_context *);
+
+#endif /* __I965_AVC_BSD_H__ */
+

i965_drv_video/i965_avc_hw_scoreboard.h

+/*
+ * Copyright © 2010 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
+ * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
+ * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ *    Xiang Haihao <haihao.xiang@intel.com>
+ *
+ */
+
+#ifndef __I965_AVC_HW_SCOREBOARD_H__
+#define __I965_AVC_HW_SCOREBOARD_H__
+
+struct i965_avc_hw_scoreboard_context
+{
+    struct {
+        unsigned int num_mb_cmds;
+        unsigned int starting_mb_number;
+        unsigned int pic_width_in_mbs;
+    } inline_data;
+
+    struct {
+        dri_bo *ss_bo;
+        dri_bo *s_bo;
+        unsigned int total_mbs;
+    } surface;
+
+    struct {
+        dri_bo *bo;
+    } binding_table;
+
+    struct {
+        dri_bo *bo;
+    } idrt;
+
+    struct {
+        dri_bo *bo;
+    } vfe_state;
+
+    struct {
+        dri_bo *bo;
+        int upload;
+    } curbe;
+
+    struct {
+        dri_bo *bo;
+        unsigned long offset;
+    } hw_kernel;
+
+    struct {
+        unsigned int vfe_start;
+        unsigned int cs_start;
+
+        unsigned int num_vfe_entries;
+        unsigned int num_cs_entries;
+
+        unsigned int size_vfe_entry;
+        unsigned int size_cs_entry;
+    } urb;
+};
+
+void i965_avc_hw_scoreboard(VADriverContextP, struct decode_state *);
+void i965_avc_hw_scoreboard_decode_init(VADriverContextP);
+Bool i965_avc_hw_scoreboard_ternimate(struct i965_avc_hw_scoreboard_context *);
+
+#endif /* __I965_AVC_HW_SCOREBOARD_H__ */
+

i965_drv_video/i965_avc_ildb.h

+/*
+ * Copyright © 2010 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
+ * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
+ * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ *    Xiang Haihao <haihao.xiang@intel.com>
+ *
+ */
+
+#ifndef __I965_AVC_ILDB_H__
+#define __I965_AVC_ILDB_H__
+
+#define SURFACE_EDGE_CONTROL_DATA       0
+#define SURFACE_SRC_Y                   1
+#define SURFACE_SRC_UV                  2
+#define SURFACE_DEST_Y                  3
+#define SURFACE_DEST_UV                 4
+
+#define NUM_AVC_ILDB_SURFACES           5
+
+#define EDGE_CONTROL_DATA_IN_DWS        16
+#define EDGE_CONTROL_DATA_IN_BTYES      64
+
+struct i965_avc_ildb_context
+{
+    struct {
+        dri_bo *bo;
+    } curbe;
+
+    struct {
+        dri_bo *ss_bo;
+        dri_bo *s_bo;
+        unsigned long offset;
+        int surface_type;
+        int width;
+        int height;
+        int depth;
+        int pitch;
+        int format;
+        int vert_line_stride;
+        int vert_line_stride_ofs;
+        int is_target;
+    } surface[NUM_AVC_ILDB_SURFACES];
+
+    struct {
+        dri_bo *bo;
+    } binding_table;
+
+    struct {
+        dri_bo *bo;
+    } idrt;
+
+    struct {
+        dri_bo *bo;
+    } vfe_state;
+
+    struct {
+        unsigned int vfe_start;
+        unsigned int cs_start;
+
+        unsigned int num_vfe_entries;
+        unsigned int num_cs_entries;
+
+        unsigned int size_vfe_entry;
+        unsigned int size_cs_entry;
+    } urb;
+
+    int picture_type;
+    int mbs_per_picture;
+};
+
+void i965_avc_ildb(VADriverContextP, struct decode_state *);
+void i965_avc_ildb_decode_init(VADriverContextP);
+Bool i965_avc_ildb_ternimate(struct i965_avc_ildb_context *);
+
+#endif /* __I965_AVC_ILDB_H__ */
+

i965_drv_video/i965_defines.h

@@ -20,6 +20,13 @@
 #define CMD_MEDIA_OBJECT                        CMD(2, 1, 0)
 #define CMD_MEDIA_OBJECT_EX                     CMD(2, 1, 1)
 
+#define CMD_AVC_BSD_IMG_STATE                   CMD(2, 4, 0)
+#define CMD_AVC_BSD_QM_STATE                    CMD(2, 4, 1)
+#define CMD_AVC_BSD_SLICE_STATE                 CMD(2, 4, 2)
+#define CMD_AVC_BSD_BUF_BASE_STATE              CMD(2, 4, 3)
+#define CMD_BSD_IND_OBJ_BASE_ADDR               CMD(2, 4, 4)
+#define CMD_AVC_BSD_OBJECT                      CMD(2, 4, 8)
+
 #define CMD_PIPELINED_POINTERS                  CMD(3, 0, 0)
 #define CMD_BINDING_TABLE_POINTERS              CMD(3, 0, 1)
 #define CMD_VERTEX_BUFFERS                      CMD(3, 0, 8)
@@ -28,6 +35,9 @@
 #define CMD_CONSTANT_COLOR                      CMD(3, 1, 1)
 #define CMD_3DPRIMITIVE                         CMD(3, 3, 0)
 
+#define CMD_DEPTH_BUFFER                        CMD(3, 1, 5)
+#define I965_DEPTHFORMAT_D32_FLOAT              1
+
 #define BASE_ADDRESS_MODIFY             (1 << 0)
 
 #define PIPELINE_SELECT_3D              0
@@ -321,6 +331,32 @@
 #define I965_TILEWALK_XMAJOR                 0
 #define I965_TILEWALK_YMAJOR                 1
 
-#define URB_SIZE(intel)         (IS_IGDNG(intel->device_id) ? 1024 : \
+#define SCAN_RASTER_ORDER       0
+#define SCAN_SPECIAL_ORDER      1
+
+#define ENTROPY_CAVLD           0
+#define ENTROPY_CABAC           1
+
+#define SLICE_TYPE_P            0
+#define SLICE_TYPE_B            1
+#define SLICE_TYPE_I            2
+#define SLICE_TYPE_SP           3
+#define SLICE_TYPE_SI           4
+
+#define PRESENT_REF_LIST0               (1 << 0)
+#define PRESENT_REF_LIST1               (1 << 1)
+#define PRESENT_WEIGHT_OFFSET_L0        (1 << 2)
+#define PRESENT_WEIGHT_OFFSET_L1        (1 << 3)
+
+#define RESIDUAL_DATA_OFFSET    48
+
+#define PRESENT_NOMV            0
+#define PRESENT_NOWO            1
+#define PRESENT_MV_WO           3
+
+#define SCOREBOARD_STALLING     0
+#define SCOREBOARD_NON_STALLING 1
+
+#define URB_SIZE(intel)         (IS_IRONLAKE(intel->device_id) ? 1024 : \
                                  IS_G4X(intel->device_id) ? 384 : 256)
 #endif /* _I965_DEFINES_H_ */

i965_drv_video/i965_drv_video.h

@@ -53,6 +53,7 @@ struct buffer_store
     unsigned char *buffer;
     dri_bo *bo;
     int ref_count;
+    int num_elements;
 };
     
 struct object_config 
@@ -64,15 +65,20 @@ struct object_config
     int num_attribs;
 };
 
+#define NUM_SLICES     10
+
 struct decode_state
 {
     struct buffer_store *pic_param;
-    struct buffer_store *slice_param;
+    struct buffer_store **slice_params;
     struct buffer_store *iq_matrix;
     struct buffer_store *bit_plane;
-    struct buffer_store *slice_data;
+    struct buffer_store **slice_datas;
     VASurfaceID current_render_target;
-    int num_slices;
+    int max_slice_params;
+    int max_slice_datas;
+    int num_slice_params;
+    int num_slice_datas;
 };
 
 struct object_context 
@@ -88,6 +94,9 @@ struct object_context
     struct decode_state decode_state;
 };
 
+#define SURFACE_REFERENCED      (1 << 0)
+#define SURFACE_DISPLAYED       (1 << 1)
+
 struct object_surface 
 {
     struct object_base base;
@@ -96,7 +105,10 @@ struct object_surface
     int width;
     int height;
     int size;
+    int flags;
     dri_bo *bo;
+    void (*free_private_data)(void **data);
+    void *private_data;
 };
 
 struct object_buffer 
@@ -129,8 +141,6 @@ struct object_subpic
     dri_bo *bo;
 };
 
-
-
 struct i965_driver_data 
 {
     struct intel_driver_data intel;

i965_drv_video/i965_media.c

@@ -38,6 +38,7 @@
 
 #include "i965_defines.h"
 #include "i965_media_mpeg2.h"
+#include "i965_media_h264.h"
 #include "i965_media.h"
 #include "i965_drv_video.h"
 
@@ -72,13 +73,21 @@ static void
 i965_media_state_base_address(VADriverContextP ctx)
 {
     struct i965_driver_data *i965 = i965_driver_data(ctx); 
+    struct i965_media_state *media_state = &i965->media_state;
 
-    if (IS_IGDNG(i965->intel.device_id)) {
+    if (IS_IRONLAKE(i965->intel.device_id)) {
         BEGIN_BATCH(ctx, 8);
         OUT_BATCH(ctx, CMD_STATE_BASE_ADDRESS | 6);
         OUT_BATCH(ctx, 0 | BASE_ADDRESS_MODIFY);
         OUT_BATCH(ctx, 0 | BASE_ADDRESS_MODIFY);
-        OUT_BATCH(ctx, 0 | BASE_ADDRESS_MODIFY);
+        
+        if (media_state->indirect_object.bo) {
+            OUT_RELOC(ctx, media_state->indirect_object.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 
+                      media_state->indirect_object.offset | BASE_ADDRESS_MODIFY);
+        } else {
+            OUT_BATCH(ctx, 0 | BASE_ADDRESS_MODIFY);
+        }
+
         OUT_BATCH(ctx, 0 | BASE_ADDRESS_MODIFY);
         OUT_BATCH(ctx, 0 | BASE_ADDRESS_MODIFY);
         OUT_BATCH(ctx, 0 | BASE_ADDRESS_MODIFY);
@@ -89,7 +98,14 @@ i965_media_state_base_address(VADriverContextP ctx)
         OUT_BATCH(ctx, CMD_STATE_BASE_ADDRESS | 4);
         OUT_BATCH(ctx, 0 | BASE_ADDRESS_MODIFY);
         OUT_BATCH(ctx, 0 | BASE_ADDRESS_MODIFY);
-        OUT_BATCH(ctx, 0 | BASE_ADDRESS_MODIFY);
+
+        if (media_state->indirect_object.bo) {
+            OUT_RELOC(ctx, media_state->indirect_object.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 
+                      media_state->indirect_object.offset | BASE_ADDRESS_MODIFY);
+        } else {
+            OUT_BATCH(ctx, 0 | BASE_ADDRESS_MODIFY);
+        }
+
         OUT_BATCH(ctx, 0 | BASE_ADDRESS_MODIFY);
         OUT_BATCH(ctx, 0 | BASE_ADDRESS_MODIFY);
         ADVANCE_BATCH(ctx);
@@ -150,6 +166,20 @@ i965_media_constant_buffer(VADriverContextP ctx, struct decode_state *decode_sta
     ADVANCE_BATCH(ctx);    
 }
 
+static void 
+i965_media_depth_buffer(VADriverContextP ctx)
+{
+    BEGIN_BATCH(ctx, 6);
+    OUT_BATCH(ctx, CMD_DEPTH_BUFFER | 4);
+    OUT_BATCH(ctx, (I965_DEPTHFORMAT_D32_FLOAT << 18) | 
+              (I965_SURFACE_NULL << 29));
+    OUT_BATCH(ctx, 0);
+    OUT_BATCH(ctx, 0);
+    OUT_BATCH(ctx, 0);
+    OUT_BATCH(ctx, 0);
+    ADVANCE_BATCH();
+}
+
 static void
 i965_media_pipeline_setup(VADriverContextP ctx, struct decode_state *decode_state)
 {
@@ -158,6 +188,7 @@ i965_media_pipeline_setup(VADriverContextP ctx, struct decode_state *decode_stat
 
     intel_batchbuffer_start_atomic(ctx, 0x1000);
     intel_batchbuffer_emit_mi_flush(ctx);                       /* step 1 */
+    i965_media_depth_buffer(ctx);
     i965_media_pipeline_select(ctx);                            /* step 2 */
     i965_media_urb_layout(ctx);                                 /* step 3 */
     i965_media_pipeline_state(ctx);                             /* step 4 */
@@ -168,7 +199,7 @@ i965_media_pipeline_setup(VADriverContextP ctx, struct decode_state *decode_stat
 }
 
 static void 
-i965_media_decode_init(VADriverContextP ctx, VAProfile profile)
+i965_media_decode_init(VADriverContextP ctx, VAProfile profile, struct decode_state *decode_state)
 {
     int i;
     struct i965_driver_data *i965 = i965_driver_data(ctx);
@@ -219,7 +250,13 @@ i965_media_decode_init(VADriverContextP ctx, VAProfile profile)
     switch (profile) {
     case VAProfileMPEG2Simple:
     case VAProfileMPEG2Main:
-        i965_media_mpeg2_decode_init(ctx);
+        i965_media_mpeg2_decode_init(ctx, decode_state);
+        break;
+        
+    case VAProfileH264Baseline:
+    case VAProfileH264Main:
+    case VAProfileH264High:
+        i965_media_h264_decode_init(ctx, decode_state);
         break;
 
     default:
@@ -236,17 +273,15 @@ i965_media_decode_picture(VADriverContextP ctx,
     struct i965_driver_data *i965 = i965_driver_data(ctx);
     struct i965_media_state *media_state = &i965->media_state;
 
-    i965_media_decode_init(ctx, profile);
-    assert(media_state->states_setup);
-    media_state->states_setup(ctx, decode_state);
+    i965_media_decode_init(ctx, profile, decode_state);
+    assert(media_state->media_states_setup);
+    media_state->media_states_setup(ctx, decode_state);
     i965_media_pipeline_setup(ctx, decode_state);
-    intel_batchbuffer_flush(ctx);
 }
 
 Bool 
 i965_media_init(VADriverContextP ctx)
 {
-    i965_media_mpeg2_init(ctx);
     return True;
 }
 
@@ -257,6 +292,9 @@ i965_media_terminate(VADriverContextP ctx)
     struct i965_media_state *media_state = &i965->media_state;
     int i;
 
+    assert(media_state->free_private_context);
+    media_state->free_private_context(&media_state->private_context);
+
     for (i = 0; i < MAX_MEDIA_SURFACES; i++) {
         dri_bo_unreference(media_state->surface_state[i].bo);
         media_state->surface_state[i].bo = NULL;
@@ -277,7 +315,9 @@ i965_media_terminate(VADriverContextP ctx)
     dri_bo_unreference(media_state->curbe.bo);
     media_state->curbe.bo = NULL;
 
-    i965_media_mpeg2_ternimate(ctx);
+    dri_bo_unreference(media_state->indirect_object.bo);
+    media_state->indirect_object.bo = NULL;
+
     return True;
 }
 

i965_drv_video/i965_media.h

@@ -38,7 +38,7 @@
 #include "i965_structs.h"
 
 #define MAX_INTERFACE_DESC      16
-#define MAX_MEDIA_SURFACES      32
+#define MAX_MEDIA_SURFACES      34
 
 #define MPEG_TOP_FIELD		1
 #define MPEG_BOTTOM_FIELD	2
@@ -82,6 +82,11 @@ struct i965_media_state
         dri_bo *bo;
     } curbe;
 
+    struct {
+        dri_bo *bo;
+        unsigned long offset;
+    } indirect_object;
+
     struct {
         unsigned int vfe_start;
         unsigned int cs_start;
@@ -93,8 +98,10 @@ struct i965_media_state
         unsigned int size_cs_entry;
     } urb;
 
-    void (*states_setup)(VADriverContextP ctx, struct decode_state *decode_state);
+    void *private_context;
+    void (*media_states_setup)(VADriverContextP ctx, struct decode_state *decode_state);
     void (*media_objects)(VADriverContextP ctx, struct decode_state *decode_state);
+    void (*free_private_context)(void **data);
 };
 
 Bool i965_media_init(VADriverContextP ctx);

i965_drv_video/i965_media_h264.h

+#ifndef _I965_MEDIA_H264_H_
+#define _I965_MEDIA_H264_H_
+
+#include "i965_avc_bsd.h"
+#include "i965_avc_hw_scoreboard.h"
+#include "i965_avc_ildb.h"
+
+#define INST_UNIT_GEN4  16
+#define INST_UNIT_GEN5  8
+
+#define MB_CMD_IN_BYTES         64
+#define MB_CMD_IN_DWS           16
+#define MB_CMD_IN_OWS           4
+
+enum {
+    H264_AVC_COMBINED = 0,
+    H264_AVC_NULL
+};
+
+struct i965_h264_context
+{
+    struct {
+        dri_bo *bo;
+        unsigned int mbs;
+    } avc_it_command_mb_info;
+
+    struct {
+        dri_bo *bo;
+        long write_offset;
+    } avc_it_data;
+
+    struct {
+        dri_bo *bo;
+    } avc_ildb_data;
+
+    struct {
+        unsigned int width_in_mbs;
+        unsigned int height_in_mbs;
+        int mbaff_frame_flag;
+    } picture;
+
+    int enable_avc_ildb;
+    int use_avc_hw_scoreboard;
+
+    int use_hw_w128;
+    unsigned int weight128_luma_l0;
+    unsigned int weight128_luma_l1;
+    unsigned int weight128_chroma_l0;
+    unsigned int weight128_chroma_l1;
+    char weight128_offset0_flag;
+    short weight128_offset0;
+
+    struct i965_avc_bsd_context i965_avc_bsd_context;
+    struct i965_avc_hw_scoreboard_context avc_hw_scoreboard_context;
+    struct i965_avc_ildb_context avc_ildb_context;
+
+    struct {
+        VASurfaceID surface_id;
+        int frame_store_id;
+    } fsid_list[16];
+};
+
+void i965_media_h264_decode_init(VADriverContextP ctx, struct decode_state *decode_state);
+
+#endif /* _I965_MEDIA_H264_H_ */

i965_drv_video/i965_media_mpeg2.c

@@ -280,7 +280,7 @@ static struct media_kernel  mpeg2_vld_kernels_gen4[] = {
     }
 };
 
-/* On IGDNG */
+/* On IRONLAKE */
 static uint32_t frame_intra_kernel_gen5[][4] = {
    #include "shaders/mpeg2/vld/frame_intra.g4b.gen5"
 };
@@ -518,6 +518,15 @@ i965_media_mpeg2_surface_setup(VADriverContextP ctx,
     int w = obj_surface->width;
     int h = obj_surface->height;
 
+    if (obj_surface->bo == NULL) {
+        struct i965_driver_data *i965 = i965_driver_data(ctx);  
+        
+        obj_surface->bo = dri_bo_alloc(i965->intel.bufmgr,
+                                       "vaapi surface",
+                                       obj_surface->size,
+                                       0x1000);
+    }
+
     if (picture_structure == MPEG_FRAME) {
 	i965_media_mpeg2_surface_state(ctx, base_index + 0, obj_surface,
 					0, w, h, 
@@ -851,107 +860,104 @@ i965_media_mpeg2_states_setup(VADriverContextP ctx, struct decode_state *decode_
 static void
 i965_media_mpeg2_objects(VADriverContextP ctx, struct decode_state *decode_state)
 {
-    int i;
+    int i, j;
     VASliceParameterBufferMPEG2 *slice_param;
 
-    assert(decode_state->slice_param && decode_state->slice_param->buffer);
-    slice_param = (VASliceParameterBufferMPEG2 *)decode_state->slice_param->buffer;
-
-    for (i = 0; i < decode_state->num_slices; i++) {
-        assert(slice_param->slice_data_flag == VA_SLICE_DATA_FLAG_ALL);
-
-        BEGIN_BATCH(ctx, 6);
-        OUT_BATCH(ctx, CMD_MEDIA_OBJECT | 4);
-        OUT_BATCH(ctx, 0);
-        OUT_BATCH(ctx, slice_param->slice_data_size - (slice_param->macroblock_offset >> 3));
-        OUT_RELOC(ctx, decode_state->slice_data->bo, 
-                  I915_GEM_DOMAIN_SAMPLER, 0, 
-                  slice_param->slice_data_offset + (slice_param->macroblock_offset >> 3));
-        OUT_BATCH(ctx, 
-                  ((slice_param->slice_horizontal_position << 24) |     
-                   (slice_param->slice_vertical_position << 16) |
-                   (127 << 8) | 
-                   (slice_param->macroblock_offset & 0x7)));
-        OUT_BATCH(ctx, slice_param->quantiser_scale_code << 24);
-        ADVANCE_BATCH(ctx);          
-        slice_param++;
+    for (j = 0; j < decode_state->num_slice_params; j++) {
+        assert(decode_state->slice_params[j] && decode_state->slice_params[j]->buffer);
+        assert(decode_state->slice_datas[j] && decode_state->slice_datas[j]->bo);
+        slice_param = (VASliceParameterBufferMPEG2 *)decode_state->slice_params[j]->buffer;
+
+        for (i = 0; i < decode_state->slice_params[j]->num_elements; i++) {
+            assert(slice_param->slice_data_flag == VA_SLICE_DATA_FLAG_ALL);
+
+            BEGIN_BATCH(ctx, 6);
+            OUT_BATCH(ctx, CMD_MEDIA_OBJECT | 4);
+            OUT_BATCH(ctx, 0);
+            OUT_BATCH(ctx, slice_param->slice_data_size - (slice_param->macroblock_offset >> 3));
+            OUT_RELOC(ctx, decode_state->slice_datas[j]->bo, 
+                      I915_GEM_DOMAIN_SAMPLER, 0, 
+                      slice_param->slice_data_offset + (slice_param->macroblock_offset >> 3));
+            OUT_BATCH(ctx, 
+                      ((slice_param->slice_horizontal_position << 24) |     
+                       (slice_param->slice_vertical_position << 16) |
+                       (127 << 8) | 
+                       (slice_param->macroblock_offset & 0x7)));
+            OUT_BATCH(ctx, slice_param->quantiser_scale_code << 24);
+            ADVANCE_BATCH(ctx);          
+            slice_param++;
+        }
     }
 }
 
-void 
-i965_media_mpeg2_decode_init(VADriverContextP ctx)
-{
-    struct i965_driver_data *i965 = i965_driver_data(ctx);
-    struct i965_media_state *media_state = &i965->media_state;
-    dri_bo *bo;
-
-    media_state->extended_state.enabled = 1;
-    dri_bo_unreference(media_state->extended_state.bo);
-    bo = dri_bo_alloc(i965->intel.bufmgr, 
-                      "vld state", 
-                      sizeof(struct i965_vld_state), 32);
-    assert(bo);
-    media_state->extended_state.bo = bo;
-
-    /* URB */
-    media_state->urb.num_vfe_entries = 28;
-    media_state->urb.size_vfe_entry = 13;
-
-    media_state->urb.num_cs_entries = 1;
-    media_state->urb.size_cs_entry = 16;
-
-    media_state->urb.vfe_start = 0;
-    media_state->urb.cs_start = media_state->urb.vfe_start + 
-        media_state->urb.num_vfe_entries * media_state->urb.size_vfe_entry;
-    assert(media_state->urb.cs_start + 
-           media_state->urb.num_cs_entries * media_state->urb.size_cs_entry <= URB_SIZE((&i965->intel)));
-
-    /* hook functions */
-    media_state->states_setup = i965_media_mpeg2_states_setup;
-    media_state->media_objects = i965_media_mpeg2_objects;
-
-}
-
-Bool 
-i965_media_mpeg2_init(VADriverContextP ctx)
+static void
+i965_media_mpeg2_free_private_context(void **data)
 {
-    struct i965_driver_data *i965 = i965_driver_data(ctx);
     int i;
 
-    /* kernel */
-    assert(NUM_MPEG2_VLD_KERNELS == (sizeof(mpeg2_vld_kernels_gen5) / 
-                                     sizeof(mpeg2_vld_kernels_gen5[0])));
-    assert(NUM_MPEG2_VLD_KERNELS <= MAX_INTERFACE_DESC);
-
-    if (IS_IGDNG(i965->intel.device_id))
-        mpeg2_vld_kernels = mpeg2_vld_kernels_gen5;
-    else
-        mpeg2_vld_kernels = mpeg2_vld_kernels_gen4;
-
     for (i = 0; i < NUM_MPEG2_VLD_KERNELS; i++) {
         struct media_kernel *kernel = &mpeg2_vld_kernels[i];
-        kernel->bo = dri_bo_alloc(i965->intel.bufmgr, 
-                                  kernel->name, 
-                                  kernel->size, 64);
-        assert(kernel->bo);
-        dri_bo_subdata(kernel->bo, 0, kernel->size, kernel->bin);
+
+        dri_bo_unreference(kernel->bo);
+        kernel->bo = NULL;
     }
 
-    return True;
+    mpeg2_vld_kernels = NULL;
 }
 
-Bool 
-i965_media_mpeg2_ternimate(VADriverContextP ctx)
+void 
+i965_media_mpeg2_decode_init(VADriverContextP ctx, struct decode_state *decode_state)
 {
+    struct i965_driver_data *i965 = i965_driver_data(ctx);
+    struct i965_media_state *media_state = &i965->media_state;
+    dri_bo *bo;
     int i;
+    if (mpeg2_vld_kernels == NULL) {
+        /* kernel */
+        assert(NUM_MPEG2_VLD_KERNELS == (sizeof(mpeg2_vld_kernels_gen5) / 
+                                         sizeof(mpeg2_vld_kernels_gen5[0])));
+        assert(NUM_MPEG2_VLD_KERNELS <= MAX_INTERFACE_DESC);
+
+        if (IS_IRONLAKE(i965->intel.device_id))
+            mpeg2_vld_kernels = mpeg2_vld_kernels_gen5;
+        else
+            mpeg2_vld_kernels = mpeg2_vld_kernels_gen4;
+
+        for (i = 0; i < NUM_MPEG2_VLD_KERNELS; i++) {
+            struct media_kernel *kernel = &mpeg2_vld_kernels[i];
+            kernel->bo = dri_bo_alloc(i965->intel.bufmgr, 
+                                      kernel->name, 
+                                      kernel->size, 64);
+            assert(kernel->bo);
+            dri_bo_subdata(kernel->bo, 0, kernel->size, kernel->bin);
+        }
 
-    for (i = 0; i < NUM_MPEG2_VLD_KERNELS; i++) {
-        struct media_kernel *kernel = &mpeg2_vld_kernels[i];
+        /* URB */
+        media_state->urb.num_vfe_entries = 28;
+        media_state->urb.size_vfe_entry = 13;
 
-        dri_bo_unreference(kernel->bo);
-        kernel->bo = NULL;
+        media_state->urb.num_cs_entries = 1;
+        media_state->urb.size_cs_entry = 16;
+
+        media_state->urb.vfe_start = 0;
+        media_state->urb.cs_start = media_state->urb.vfe_start + 
+            media_state->urb.num_vfe_entries * media_state->urb.size_vfe_entry;
+        assert(media_state->urb.cs_start + 
+               media_state->urb.num_cs_entries * media_state->urb.size_cs_entry <= URB_SIZE((&i965->intel)));
+
+        /* hook functions */
+        media_state->media_states_setup = i965_media_mpeg2_states_setup;
+        media_state->media_objects = i965_media_mpeg2_objects;
+        media_state->free_private_context = i965_media_mpeg2_free_private_context;
     }
 
-    return True;
+    media_state->extended_state.enabled = 1;
+    media_state->indirect_object.bo = NULL;
+    dri_bo_unreference(media_state->extended_state.bo);
+    bo = dri_bo_alloc(i965->intel.bufmgr, 
+                      "vld state", 
+                      sizeof(struct i965_vld_state), 32);
+    assert(bo);
+    media_state->extended_state.bo = bo;
 }
 

i965_drv_video/i965_media_mpeg2.h

@@ -39,8 +39,6 @@
 
 struct decode_state;
 
-Bool i965_media_mpeg2_init(VADriverContextP ctx);
-Bool i965_media_mpeg2_ternimate(VADriverContextP ctx);
-void i965_media_mpeg2_decode_init(VADriverContextP ctx);
+void i965_media_mpeg2_decode_init(VADriverContextP ctx, struct decode_state * decode_state);
 
 #endif /* _I965_MEDIA_MPEG2_H_ */

i965_drv_video/i965_render.h

@@ -43,7 +43,6 @@ struct i965_render_state
     
     struct {
         dri_bo *state;
-        dri_bo *prog;
     } sf;
 
     struct {
@@ -52,7 +51,6 @@ struct i965_render_state
         dri_bo *surface[MAX_RENDER_SURFACES];
         dri_bo *binding_table;
         dri_bo *state;
-        dri_bo *prog;
     } wm;
 
     struct {
@@ -60,6 +58,12 @@ struct i965_render_state
         dri_bo *viewport;
     } cc;
 
+    struct {
+        dri_bo *bo;
+        int upload;
+    } curbe;
+
+    int interleaved_uv;
     struct intel_region *draw_region;
 };
 

i965_drv_video/i965_structs.h

@@ -34,16 +34,20 @@ struct i965_vfe_state_ex
 	unsigned int obj_id:24;
     } vfex0;
 
-    struct {
-	unsigned int residual_grf_offset:5;
-	unsigned int pad0:3;
-	unsigned int weight_grf_offset:5;
-	unsigned int pad1:3;
-	unsigned int residual_data_offset:8;
-	unsigned int sub_field_present_flag:2;
-	unsigned int residual_data_fix_offset:1;
-	unsigned int pad2:5;
-    }vfex1;
+    union {
+        struct {
+            unsigned int residual_grf_offset:5;
+            unsigned int pad0:3;
+            unsigned int weight_grf_offset:5;
+            unsigned int pad1:3;
+            unsigned int residual_data_offset:8;
+            unsigned int sub_field_present_flag:2;
+            unsigned int residual_data_fix_offset_flag:1;
+            unsigned int pad2:5;
+        } avc;
+        
+        unsigned int vc1;
+    } vfex1;
 
     struct {
 	unsigned int remap_index_0:4;
@@ -68,18 +72,32 @@ struct i965_vfe_state_ex
     } remap_table1;
 
     struct {
-	unsigned int scoreboard_mask:8;
+	unsigned int mask:8;
 	unsigned int pad:22;
 	unsigned int type:1;
 	unsigned int enable:1;
     } scoreboard0;
 
     struct {
-	unsigned int ignore;
+        int delta_x0:4;
+        int delta_y0:4;
+        int delta_x1:4;
+        int delta_y1:4;
+        int delta_x2:4;
+        int delta_y2:4;
+        int delta_x3:4;
+        int delta_y3:4;
     } scoreboard1;
 
     struct {
-	unsigned int ignore;
+        int delta_x4:4;
+        int delta_y4:4;
+        int delta_x5:4;
+        int delta_y5:4;
+        int delta_x6:4;
+        int delta_y6:4;
+        int delta_x7:4;
+        int delta_y7:4;
     } scoreboard2;
 
     unsigned int pad;
@@ -177,8 +195,9 @@ struct i965_surface_state
 	unsigned int cube_neg_y:1;
 	unsigned int cube_pos_x:1;
 	unsigned int cube_neg_x:1;
-	unsigned int pad:3;
+	unsigned int pad:2;
 	unsigned int render_cache_read_mode:1;
+	unsigned int cube_map_corner_mode:1;
 	unsigned int mipmap_layout_mode:1;
 	unsigned int vert_line_stride_ofs:1;
 	unsigned int vert_line_stride:1;

i965_drv_video/intel_batchbuffer.h

@@ -16,10 +16,16 @@ struct intel_batchbuffer
     unsigned char *map;
     unsigned char *ptr;
     int atomic;
+    int flag;
+
+    int (*run)(drm_intel_bo *bo, int used,
+               drm_clip_rect_t *cliprects, int num_cliprects,
+               int DR4, int ring_flag);
 };
 
 Bool intel_batchbuffer_init(struct intel_driver_data *intel);
 Bool intel_batchbuffer_terminate(struct intel_driver_data *intel);
+
 void intel_batchbuffer_emit_dword(VADriverContextP ctx, unsigned int x);
 void intel_batchbuffer_emit_reloc(VADriverContextP ctx, dri_bo *bo, 
                                   uint32_t read_domains, uint32_t write_domains, 
@@ -31,6 +37,17 @@ void intel_batchbuffer_start_atomic(VADriverContextP ctx, unsigned int size);
 void intel_batchbuffer_end_atomic(VADriverContextP ctx);
 Bool intel_batchbuffer_flush(VADriverContextP ctx);
 
+void intel_batchbuffer_emit_dword_bcs(VADriverContextP ctx, unsigned int x);
+void intel_batchbuffer_emit_reloc_bcs(VADriverContextP ctx, dri_bo *bo, 
+                                      uint32_t read_domains, uint32_t write_domains, 
+                                      uint32_t delta);
+void intel_batchbuffer_require_space_bcs(VADriverContextP ctx, unsigned int size);
+void intel_batchbuffer_data_bcs(VADriverContextP ctx, void *data, unsigned int size);
+void intel_batchbuffer_emit_mi_flush_bcs(VADriverContextP ctx);
+void intel_batchbuffer_start_atomic_bcs(VADriverContextP ctx, unsigned int size);
+void intel_batchbuffer_end_atomic_bcs(VADriverContextP ctx);
+Bool intel_batchbuffer_flush_bcs(VADriverContextP ctx);
+
 #define BEGIN_BATCH(ctx, n) do {                                \
    intel_batchbuffer_require_space(ctx, (n) * 4);               \
 } while (0)
@@ -48,4 +65,21 @@ Bool intel_batchbuffer_flush(VADriverContextP ctx);
 #define ADVANCE_BATCH(ctx) do {                                         \
 } while (0)
 
+#define BEGIN_BCS_BATCH(ctx, n) do {                                    \
+   intel_batchbuffer_require_space_bcs(ctx, (n) * 4);                   \
+} while (0)
+
+#define OUT_BCS_BATCH(ctx, d) do {                                      \
+   intel_batchbuffer_emit_dword_bcs(ctx, d);                            \
+} while (0)
+
+#define OUT_BCS_RELOC(ctx, bo, read_domains, write_domain, delta) do {  \
+   assert((delta) >= 0);                                                \
+   intel_batchbuffer_emit_reloc_bcs(ctx, bo,                            \
+                                    read_domains, write_domain, delta); \
+} while (0)
+
+#define ADVANCE_BCS_BATCH(ctx) do {                                     \
+} while (0)
+
 #endif /* _INTEL_BATCHBUFFER_H_ */

i965_drv_video/intel_batchbuffer_dump.h

+#ifndef _INTEL_BATCHBUFFER_DUMP_H_
+#define _INTEL_BATCHBUFFER_DUMP_H_
+
+#define MASK_CMD_TYPE           0xE0000000
+
+#define SHIFT_CMD_TYPE          29
+
+#define CMD_TYPE_GFXPIPE        3
+#define CMD_TYPE_BLT            2
+#define CMD_TYPE_MI             0
+
+
+/* GFXPIPE */
+#define MASK_GFXPIPE_SUBTYPE    0x18000000
+#define MASK_GFXPIPE_OPCODE     0x07000000
+#define MASK_GFXPIPE_SUBOPCODE  0x00FF0000
+#define MASK_GFXPIPE_LENGTH     0x0000FFFF
+
+#define SHIFT_GFXPIPE_SUBTYPE           27
+#define SHIFT_GFXPIPE_OPCODE            24
+#define SHIFT_GFXPIPE_SUBOPCODE         16
+#define SHIFT_GFXPIPE_LENGTH            0
+
+/* 3D */
+#define GFXPIPE_3D              3
+
+/* BSD */
+#define GFXPIPE_BSD             2
+
+#define OPCODE_BSD_AVC          4
+
+#define SUBOPCODE_BSD_IMG       0
+#define SUBOPCODE_BSD_QM        1
+#define SUBOPCODE_BSD_SLICE     2
+#define SUBOPCODE_BSD_BUF_BASE  3
+#define SUBOPCODE_BSD_IND_OBJ   4
+#define SUBOPCODE_BSD_OBJECT    8
+
+/* MI */
+#define MASK_MI_OPCODE          0x1F800000
+
+#define SHIFT_MI_OPCODE         23
+
+#define OPCODE_MI_FLUSH                 0x04
+#define OPCODE_MI_BATCH_BUFFER_END      0x0A
+
+int intel_batchbuffer_dump(unsigned int *data, unsigned int offset, int count, unsigned int device);
+
+#endif /* _INTEL_BATCHBUFFER_DUMP_H_ */

i965_drv_video/intel_driver.h

@@ -26,6 +26,7 @@
 #define MI_NOOP                                 (CMD_MI | 0)
 
 #define MI_BATCH_BUFFER_END                     (CMD_MI | (0xA << 23))
+#define MI_BATCH_BUFFER_START                   (CMD_MI | (0x31 << 23))
 
 #define MI_FLUSH                                (CMD_MI | (0x4 << 23))
 #define STATE_INSTRUCTION_CACHE_INVALIDATE      (0x1 << 0)
@@ -44,6 +45,7 @@ struct intel_batchbuffer;
 #define ALIGN(i, n)    (((i) + (n) - 1) & ~((n) - 1))
 #define MIN(a, b) ((a) < (b) ? (a) : (b))
 #define MAX(a, b) ((a) > (b) ? (a) : (b))
+#define ARRAY_ELEMS(a) (sizeof(a) / sizeof((a)[0]))
 
 #define SET_BLOCKED_SIGSET()   do {     \
         sigset_t bl_mask;               \
@@ -85,6 +87,7 @@ struct intel_driver_data
     int locked;
 
     struct intel_batchbuffer *batch;
+    struct intel_batchbuffer *batch_bcs;
     dri_bufmgr *bufmgr;
 };
 
@@ -118,8 +121,8 @@ struct intel_region
 #define PCI_CHIP_G45_G                  0x2E22
 #define PCI_CHIP_G41_G                  0x2E32
 
-#define PCI_CHIP_IGDNG_D_G              0x0042
-#define PCI_CHIP_IGDNG_M_G              0x0046
+#define PCI_CHIP_IRONLAKE_D_G           0x0042
+#define PCI_CHIP_IRONLAKE_M_G           0x0046
 
 #define IS_G45(devid)           (devid == PCI_CHIP_IGD_E_G || \
                                  devid == PCI_CHIP_Q45_G || \
@@ -128,8 +131,8 @@ struct intel_region
 #define IS_GM45(devid)          (devid == PCI_CHIP_GM45_GM)
 #define IS_G4X(devid)		(IS_G45(devid) || IS_GM45(devid))
 
-#define IS_IGDNG_D(devid)       (devid == PCI_CHIP_IGDNG_D_G)
-#define IS_IGDNG_M(devid)       (devid == PCI_CHIP_IGDNG_M_G)
-#define IS_IGDNG(devid)         (IS_IGDNG_D(devid) || IS_IGDNG_M(devid))
+#define IS_IRONLAKE_D(devid)    (devid == PCI_CHIP_IRONLAKE_D_G)
+#define IS_IRONLAKE_M(devid)    (devid == PCI_CHIP_IRONLAKE_M_G)
+#define IS_IRONLAKE(devid)      (IS_IRONLAKE_D(devid) || IS_IRONLAKE_M(devid))
 
 #endif /* _INTEL_DRIVER_H_ */

i965_drv_video/object_heap.c

@@ -50,7 +50,6 @@ static int object_heap_expand( object_heap_p heap )
     {
         return -1; /* Out of memory */
     }
-    memset(new_heap_index + heap->heap_size*heap->object_size, 0, heap->heap_increment * new_heap_size);
     heap->heap_index = new_heap_index;
     next_free = heap->next_free;
     for(i = new_heap_size; i-- > heap->heap_size; )

i965_drv_video/shaders/Makefile.am

-SUBDIRS = mpeg2 render
+SUBDIRS = h264 mpeg2 render

i965_drv_video/shaders/h264/Makefile.am

+SUBDIRS = mc

i965_drv_video/shaders/h264/ildb/AVC_ILDB_Child_Field_UV.asm

+/*
+ * Copyright © <2010>, Intel Corporation.
+ *
+ * This program is licensed under the terms and conditions of the
+ * Eclipse Public License (EPL), version 1.0.  The full text of the EPL is at
+ * http://www.opensource.org/licenses/eclipse-1.0.php.
+ *
+ */
+#include "AVC_ILDB_Child_UV.asm"

i965_drv_video/shaders/h264/ildb/AVC_ILDB_Child_Field_Y.asm

+/*
+ * Copyright © <2010>, Intel Corporation.
+ *
+ * This program is licensed under the terms and conditions of the
+ * Eclipse Public License (EPL), version 1.0.  The full text of the EPL is at
+ * http://www.opensource.org/licenses/eclipse-1.0.php.
+ *
+ */
+#include "AVC_ILDB_Child_Y.asm"

i965_drv_video/shaders/h264/ildb/AVC_ILDB_CloseGateway.asm

+/*
+ * Copyright © <2010>, Intel Corporation.
+ *
+ * This program is licensed under the terms and conditions of the
+ * Eclipse Public License (EPL), version 1.0.  The full text of the EPL is at
+ * http://www.opensource.org/licenses/eclipse-1.0.php.
+ *
+ */
+//----- Close a Message Gateway -----
+
+#if defined(_DEBUG) 
+	mov		(1)		EntrySignature:b			0x4444:w
+#endif
+
+// Message descriptor
+// bit 31	EOD
+// 27:24	FFID = 0x0011 for msg gateway
+// 23:20	msg length = 1 MRF
+// 19:16	Response length	= 0
+// 1:0		SubFuncID = 01 for CloseGateway
+// Message descriptor: 0 000 0011 0001 0000 + 0 0 000000000000 01 ==> 0000 0011 0001 0000 0000 0000 0000 0001
+send (8)	null:ud 	m7	  r0.0<0;1,0>:ud    MSG_GW	CGWMSGDSC 

i965_drv_video/shaders/h264/ildb/AVC_ILDB_ForwardMsg.asm

+/*
+ * Copyright © <2010>, Intel Corporation.
+ *
+ * This program is licensed under the terms and conditions of the
+ * Eclipse Public License (EPL), version 1.0.  The full text of the EPL is at
+ * http://www.opensource.org/licenses/eclipse-1.0.php.
+ *
+ */
+//========== Forward message to root thread through gateway ==========
+// Each child thread write a byte into the root GRF r50 defiend in open Gataway.
+
+#if defined(_DEBUG) 
+mov		(1)		EntrySignatureC:w			0x7777:w
+#endif
+
+// Init payload to r0
+mov (8) 	GatewayPayload<1>:ud 	0:w								//{ NoDDClr } 
+
+// Forward a message:
+// Offset = x relative to r50 (defiend in open gataway), x = ORIX >> 4 [bit 28:16]
+// Need to shift left 16
+
+// shift 2 more bits for byte to word offset
+
+//shl	(1)		Offset_Length:ud		GateWayOffsetC:w	 	16:w		{ NoDDClr, NoDDChk }
+shl	(1)		Offset_Length:ud		GateWayOffsetC:w	 	18:w		
+
+// 2 bytes offset
+add	(1)		Offset_Length:ud			Offset_Length:ud		0x00020000:d	{ NoDDClr }
+	
+// Length = 1 byte,	[bit 10:8 = 000]
+//000 xxxxxxxxxxxxx 00000 000 00000000 ==> 000x xxxx xxxx xxxx 0000 0000 0000 0000
+
+//mov (1) 	DispatchID:ub 			r0.20:ub		// Dispatch ID
+
+//Move in EUid and Thread ID that we received from the PARENT thread
+mov (1) 	EUID_TID:uw 			r0.6:uw								{ NoDDClr, NoDDChk }
+
+mov (1) 	GatewayPayloadKey:uw 	0x1212:uw							{ NoDDClr, NoDDChk }	// Key
+
+//mov	(4)		GatewayPayload<1>:ud	0:ud								{ NoDDClr, NoDDChk }	// Init payload low 4 dword
+
+// Write back one byte (value = 0xFF) to root thread GRF to indicate this child thread is finished
+// All lower 4 bytes must be assigned to the same byte value.
+mov	(4)		GatewayPayload<1>:ub	0xFFFF:uw							{ NoDDChk }
+
+// msg descriptor bit 15 set to '1' for notification
+#ifdef GW_DCN
+// For ILK, EOT bit should also be set to terminate the thread. This is to fix a timing related HW issue.
+//
+send (8)  	null:ud 		m0	  		GatewayPayload<8;8,1>:ud    MSG_GW_EOT	FWDMSGDSC+NOTIFYMSG
+#else
+send (8)  	null:ud 		m0	  		GatewayPayload<8;8,1>:ud    MSG_GW	FWDMSGDSC+NOTIFYMSG
+#endif	// GW_DCN
+
+//========== Forward Msg Done ========================================
+

i965_drv_video/shaders/h264/ildb/AVC_ILDB_LumaThrdLimit.asm

+/*
+ * Copyright © <2010>, Intel Corporation.
+ *
+ * This program is licensed under the terms and conditions of the
+ * Eclipse Public License (EPL), version 1.0.  The full text of the EPL is at
+ * http://www.opensource.org/licenses/eclipse-1.0.php.
+ *
+ */
+//========== Forward message to root thread through gateway ==========
+
+// Chroma root kenrel updates luma thread limit.
+
+#if defined(_DEBUG) 
+mov		(1)		EntrySignatureC:w			0x7788:w
+#endif
+
+// Init payload to r0
+mov (8) 	GatewayPayload<1>:ud 	0:w								{ NoDDClr } 
+
+// Forward a message:
+// Offset = x relative to r50 (defiend in open gataway), x = ORIX >> 4 [bit 28:16]
+// Need to shift left 16
+
+mov	(1)		Offset_Length:ud		THREAD_LIMIT_OFFSET:ud	 			{ NoDDClr, NoDDChk }
+
+// Length = 1 byte,	[bit 10:8 = 000]
+//000 xxxxxxxxxxxxx 00000 000 00000000 ==> 000x xxxx xxxx xxxx 0000 0000 0000 0000
+
+//mov (1) 	DispatchID:ub 			r0.20:ub		// Dispatch ID
+
+//  Copy EUid and Thread ID that we received from the PARENT thread
+mov (1) 	EUID_TID:uw 			r0.6:uw								{ NoDDClr, NoDDChk }
+
+mov (1) 	GatewayPayloadKey:uw 	0x1212:uw							{ NoDDChk }	// Key
+
+//mov	(4)		GatewayPayload<1>:ud	0:ud								{ NoDDClr, NoDDChk }	// Init payload low 4 dword
+
+// Write back one byte (value = 0xFF) to root thread GRF to indicate this child thread is finished
+// All lower 4 bytes must be assigned to the same byte value.
+add	(1)		Temp1_W:w				MaxThreads:uw	-OutstandingThreads:uw
+mov	(4)		GatewayPayload<1>:ub	Temp1_B<0;1,0>:ub 
+
+send (8)  	GatewayResponse:ud 		m0	  		GatewayPayload<8;8,1>:ud    MSG_GW	FWDMSGDSC
+
+//========== Forward Msg Done ========================================
+

i965_drv_video/shaders/h264/ildb/AVC_ILDB_Root_Field_UV.asm

+/*
+ * Copyright © <2010>, Intel Corporation.
+ *
+ * This program is licensed under the terms and conditions of the
+ * Eclipse Public License (EPL), version 1.0.  The full text of the EPL is at
+ * http://www.opensource.org/licenses/eclipse-1.0.php.
+ *
+ */
+#include "AVC_ILDB_Root_UV.asm"