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Commit 2704b998 authored by Zhou Chang's avatar Zhou Chang Committed by Xiang, Haihao
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i965_drv_video: improved MV quality for VME

parent d06d49a5
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Showing with 39 additions and 61 deletions
i965_drv_video/gen6_vme.c
View file @ 2704b998
...@@ -425,10 +425,19 @@ static VAStatus gen6_vme_vme_state_setup(VADriverContextP ctx, ...@@ -425,10 +425,19 @@ static VAStatus gen6_vme_vme_state_setup(VADriverContextP ctx,
assert(vme_context->vme_state.bo->virtual); assert(vme_context->vme_state.bo->virtual);
vme_state_message = (unsigned int *)vme_context->vme_state.bo->virtual; vme_state_message = (unsigned int *)vme_context->vme_state.bo->virtual;
for(i = 0;i < 32; i++) { vme_state_message[0] = 0x10010101;
vme_state_message[i] = 0x11; vme_state_message[1] = 0x100F0F0F;
} vme_state_message[2] = 0x10010101;
vme_state_message[16] = 0x42424242; //cost function LUT set 0 for Intra vme_state_message[3] = 0x000F0F0F;
for(i = 4; i < 14; i++) {
vme_state_message[i] = 0x00000000;
}
for(i = 14; i < 32; i++) {
vme_state_message[i] = 0x00000000;
}
//vme_state_message[16] = 0x42424242; //cost function LUT set 0 for Intra
dri_bo_unmap( vme_context->vme_state.bo); dri_bo_unmap( vme_context->vme_state.bo);
return VA_STATUS_SUCCESS; return VA_STATUS_SUCCESS;
......
i965_drv_video/shaders/vme/inter_frame.asm
View file @ 2704b998
...@@ -24,65 +24,30 @@ __INTER_START: ...@@ -24,65 +24,30 @@ __INTER_START:
mov (16) tmp_reg0.0<1>:UD 0x0:UD {align1}; mov (16) tmp_reg0.0<1>:UD 0x0:UD {align1};
mov (16) tmp_reg2.0<1>:UD 0x0:UD {align1}; mov (16) tmp_reg2.0<1>:UD 0x0:UD {align1};
/*
* Media Read Message -- fetch neighbor edge pixels
*/
/* ROW */
// mul (2) tmp_reg0.0<1>:D orig_xy_ub<2,2,1>:UB 16:UW {align1}; /* (x, y) * 16 */
// add (1) tmp_reg0.0<1>:D tmp_reg0.0<0,1,0>:D -8:W {align1}; /* X offset */
// add (1) tmp_reg0.4<1>:D tmp_reg0.4<0,1,0>:D -1:W {align1}; /* Y offset */
// mov (1) tmp_reg0.8<1>:UD BLOCK_32X1 {align1};
// mov (1) tmp_reg0.20<1>:UB thread_id_ub {align1}; /* dispatch id */
// mov (8) msg_reg0.0<1>:UD tmp_reg0.0<8,8,1>:UD {align1};
// send (16) 0 INEP_ROW null read(BIND_IDX_INEP, 0, 0, 4) mlen 1 rlen 1 {align1};
/* COL */
// mul (2) tmp_reg0.0<1>:D orig_xy_ub<2,2,1>:UB 16:UW {align1}; /* (x, y) * 16 */
// add (1) tmp_reg0.0<1>:D tmp_reg0.0<0,1,0>:D -4:W {align1}; /* X offset */
// mov (1) tmp_reg0.8<1>:UD BLOCK_4X16 {align1};
// mov (1) tmp_reg0.20<1>:UB thread_id_ub {align1}; /* dispatch id */
// mov (8) msg_reg0.0<1>:UD tmp_reg0.0<8,8,1>:UD {align1};
// send (16) 0 INEP_COL0 null read(BIND_IDX_INEP, 0, 0, 4) mlen 1 rlen 2 {align1};
/* /*
* VME message * VME message
*/ */
/* m0 */ /* m0 */
mul (2) tmp_reg0.0<1>:UW orig_xy_ub<2,2,1>:UB 16:UW {align1}; /* (x, y) * 16 */ mul (2) tmp_reg0.8<1>:UW orig_xy_ub<2,2,1>:UB 16:UW {align1}; /* Source = (x, y) * 16 */
mov (1) tmp_reg0.8<1>:UD tmp_reg0.0<0,1,0>:UD {align1}; mul (2) tmp_reg0.0<1>:UW orig_xy_ub<2,2,1>:UB 16:UW {align1};
mov (1) tmp_reg0.12<1>:UD INTER_SAD_HAAR + INTRA_SAD_HAAR + SUB_PEL_MODE_QUARTER:UD {align1}; /* 16x16 Source, 1/4 pixel, harr */ add (2) tmp_reg0.0<1>:W tmp_reg0.0<2,2,1>:W -8:W {align1}; /* Reference = (x-8,y-8)-(x+24,y+24) */
mov (1) tmp_reg0.12<1>:UD INTER_PART_MASK + INTER_SAD_HAAR + SUB_PEL_MODE_QUARTER:UD {align1}; /* 16x16 Source, 1/4 pixel, harr */
mov (1) tmp_reg0.20<1>:UB thread_id_ub {align1}; /* dispatch id */ mov (1) tmp_reg0.20<1>:UB thread_id_ub {align1}; /* dispatch id */
mov (1) tmp_reg0.22<1>:UW REF_REGION_SIZE {align1}; /* Reference Width&Height, 32x32 */ mov (1) tmp_reg0.22<1>:UW REF_REGION_SIZE {align1}; /* Reference Width&Height, 32x32 */
mov (8) msg_reg0.0<1>:UD tmp_reg0.0<8,8,1>:UD {align1}; mov (8) msg_reg0.0<1>:UD tmp_reg0.0<8,8,1>:UD {align1};
/* m1 */ /* m1 */
mov (1) tmp_reg1.4<1>:UD BI_SUB_MB_PART_MASK + MAX_NUM_MV:UD {align1}; /* Default value MAX 32 MVs */ mov (1) tmp_reg1.4<1>:UD MAX_NUM_MV:UD {align1}; /* Default value MAX 32 MVs */
mov (1) tmp_reg1.8<1>:UD SEARCH_PATH_LEN:UD {align1};
mov (1) intra_part_mask_ub<1>:UB LUMA_INTRA_8x8_DISABLE + LUMA_INTRA_4x4_DISABLE {align1};
// cmp.nz.f0.0 (1) null<1>:UW orig_x_ub<0,1,0>:UB 0:UW {align1}; /* X != 0 */
// (f0.0) add (1) mb_intra_struct_ub<1>:UB mb_intra_struct_ub<0,1,0>:UB INTRA_PRED_AVAIL_FLAG_AE {align1}; /* A */
// cmp.nz.f0.0 (1) null<1>:UW orig_y_ub<0,1,0>:UB 0:UW {align1}; /* Y != 0 */
// (f0.0) add (1) mb_intra_struct_ub<1>:UB mb_intra_struct_ub<0,1,0>:UB INTRA_PRED_AVAIL_FLAG_B {align1}; /* B */
// mul.nz.f0.0 (1) null<1>:UW orig_x_ub<0,1,0>:UB orig_y_ub<0,1,0>:UB {align1}; /* X * Y != 0 */
// (f0.0) add (1) mb_intra_struct_ub<1>:UB mb_intra_struct_ub<0,1,0>:UB INTRA_PRED_AVAIL_FLAG_D {align1}; /* D */
// add (1) tmp_x_w<1>:W orig_x_ub<0,1,0>:UB 1:UW {align1}; /* X + 1 */
// add (1) tmp_x_w<1>:W w_in_mb_uw<0,1,0>:UW -tmp_x_w<0,1,0>:W {align1}; /* width - (X + 1) */
// mul.nz.f0.0 (1) null<1>:UD tmp_x_w<0,1,0>:W orig_y_ub<0,1,0>:UB {align1}; /* (width - (X + 1)) * Y != 0 */
// (f0.0) add (1) mb_intra_struct_ub<1>:UB mb_intra_struct_ub<0,1,0>:UB INTRA_PRED_AVAIL_FLAG_C {align1}; /* C */
mov (8) msg_reg1<1>:UD tmp_reg1.0<8,8,1>:UD {align1}; mov (8) msg_reg1<1>:UD tmp_reg1.0<8,8,1>:UD {align1};
/* m2 */ /* m2 */
mov (8) msg_reg2<1>:UD INEP_ROW.0<8,8,1>:UD {align1}; mov (8) msg_reg2<1>:UD 0x0:UD {align1};
/* m3 */ /* m3 */
mov (8) msg_reg3<1>:UD 0x0 {align1}; mov (8) msg_reg3<1>:UD 0x0:UD {align1};
mov (16) msg_reg3.0<1>:UB INEP_COL0.3<32,8,4>:UB {align1};
mov (1) msg_reg3.16<1>:UD INTRA_PREDICTORE_MODE {align1};
send (8) 0 vme_wb null vme(BIND_IDX_VME,0,0,VME_MESSAGE_TYPE_INTER) mlen 4 rlen 4 {align1}; send (8) 0 vme_wb null vme(BIND_IDX_VME,0,0,VME_MESSAGE_TYPE_INTER) mlen 4 rlen 4 {align1};
...@@ -96,10 +61,11 @@ mov (1) tmp_reg3.20<1>:UB thread_id_ub {align1}; /* dispa ...@@ -96,10 +61,11 @@ mov (1) tmp_reg3.20<1>:UB thread_id_ub {align1}; /* dispa
mov (8) msg_reg0.0<1>:UD tmp_reg3.0<8,8,1>:UD {align1}; mov (8) msg_reg0.0<1>:UD tmp_reg3.0<8,8,1>:UD {align1};
mov (2) tmp_reg3.0<1>:UW vme_wb1.0<2,2,1>:UB {align1}; mov (2) tmp_reg3.0<1>:UW vme_wb1.0<2,2,1>:UB {align1};
add (2) tmp_reg3.0<1>:W tmp_reg3.0<16,16,1>:W -32:W {align1};
mov (8) msg_reg1.0<1>:UD tmp_reg3.0<0,1,0>:UD {align1}; mov (8) msg_reg1.0<1>:UD tmp_reg3.0<8,8,0>:UD {align1};
mov (8) msg_reg2.0<1>:UD tmp_reg3.0<0,1,0>:UD {align1}; mov (8) msg_reg2.0<1>:UD tmp_reg3.0<8,8,0>:UD {align1};
/* bind index 3, write 4 oword, msg type: 8(OWord Block Write) */ /* bind index 3, write 4 oword, msg type: 8(OWord Block Write) */
send (16) 0 obw_wb null write(BIND_IDX_OUTPUT, 3, 8, 1) mlen 3 rlen 1 {align1}; send (16) 0 obw_wb null write(BIND_IDX_OUTPUT, 3, 8, 1) mlen 3 rlen 1 {align1};
......
i965_drv_video/shaders/vme/inter_frame.g6b
View file @ 2704b998
{ 0x00800001, 0x24000061, 0x00000000, 0x00000000 }, { 0x00800001, 0x24000061, 0x00000000, 0x00000000 },
{ 0x00800001, 0x24400061, 0x00000000, 0x00000000 }, { 0x00800001, 0x24400061, 0x00000000, 0x00000000 },
{ 0x00200041, 0x24082e29, 0x004500a0, 0x00100010 },
{ 0x00200041, 0x24002e29, 0x004500a0, 0x00100010 }, { 0x00200041, 0x24002e29, 0x004500a0, 0x00100010 },
{ 0x00000001, 0x24080021, 0x00000400, 0x00000000 }, { 0x00200040, 0x24003dad, 0x00450400, 0xfff8fff8 },
{ 0x00000001, 0x240c0061, 0x00000000, 0x00a03000 }, { 0x00000001, 0x240c0061, 0x00000000, 0x7e203000 },
{ 0x00000001, 0x24140231, 0x00000014, 0x00000000 }, { 0x00000001, 0x24140231, 0x00000014, 0x00000000 },
{ 0x00000001, 0x24160169, 0x00000000, 0x20202020 }, { 0x00000001, 0x24160169, 0x00000000, 0x20202020 },
{ 0x00600001, 0x20000022, 0x008d0400, 0x00000000 }, { 0x00600001, 0x20000022, 0x008d0400, 0x00000000 },
{ 0x00000001, 0x24240061, 0x00000000, 0x0c000020 }, { 0x00000001, 0x24240061, 0x00000000, 0x00000020 },
{ 0x00000001, 0x243c00f1, 0x00000000, 0x00000006 }, { 0x00000001, 0x24280061, 0x00000000, 0x00003f3f },
{ 0x00600001, 0x20200022, 0x008d0420, 0x00000000 }, { 0x00600001, 0x20200022, 0x008d0420, 0x00000000 },
{ 0x00600001, 0x20400022, 0x008d0240, 0x00000000 }, { 0x00600001, 0x20400062, 0x00000000, 0x00000000 },
{ 0x00600001, 0x206000e2, 0x00000000, 0x00000000 }, { 0x00600001, 0x20600062, 0x00000000, 0x00000000 },
{ 0x00800001, 0x20600232, 0x00cf0283, 0x00000000 },
{ 0x00000001, 0x20700062, 0x00000000, 0x11111111 },
{ 0x08600031, 0x21801cdd, 0x00000000, 0x08482000 }, { 0x08600031, 0x21801cdd, 0x00000000, 0x08482000 },
{ 0x00000041, 0x24684521, 0x000000a2, 0x000000a1 }, { 0x00000041, 0x24684521, 0x000000a2, 0x000000a1 },
{ 0x00000040, 0x24684421, 0x00000468, 0x000000a0 }, { 0x00000040, 0x24684421, 0x00000468, 0x000000a0 },
...@@ -20,8 +19,9 @@ ...@@ -20,8 +19,9 @@
{ 0x00000001, 0x24740231, 0x00000014, 0x00000000 }, { 0x00000001, 0x24740231, 0x00000014, 0x00000000 },
{ 0x00600001, 0x20000022, 0x008d0460, 0x00000000 }, { 0x00600001, 0x20000022, 0x008d0460, 0x00000000 },
{ 0x00200001, 0x24600229, 0x004501a0, 0x00000000 }, { 0x00200001, 0x24600229, 0x004501a0, 0x00000000 },
{ 0x00600001, 0x20200022, 0x00000460, 0x00000000 }, { 0x00200040, 0x24603dad, 0x00b10460, 0xffe0ffe0 },
{ 0x00600001, 0x20400022, 0x00000460, 0x00000000 }, { 0x00600001, 0x20200022, 0x008c0460, 0x00000000 },
{ 0x00600001, 0x20400022, 0x008c0460, 0x00000000 },
{ 0x05800031, 0x22001cdd, 0x00000000, 0x061b0303 }, { 0x05800031, 0x22001cdd, 0x00000000, 0x061b0303 },
{ 0x00600001, 0x20000022, 0x008d0000, 0x00000000 }, { 0x00600001, 0x20000022, 0x008d0000, 0x00000000 },
{ 0x07800031, 0x24001cc8, 0x00000000, 0x82000010 }, { 0x07800031, 0x24001cc8, 0x00000000, 0x82000010 },
i965_drv_video/shaders/vme/vme_header.inc
View file @ 2704b998
...@@ -46,11 +46,14 @@ define(`INTER_SAD_HAAR', `0x00200000') ...@@ -46,11 +46,14 @@ define(`INTER_SAD_HAAR', `0x00200000')
define(`INTRA_SAD_NONE', `0x00000000') define(`INTRA_SAD_NONE', `0x00000000')
define(`INTRA_SAD_HAAR', `0x00800000') define(`INTRA_SAD_HAAR', `0x00800000')
define(`INTER_PART_MASK', `0x7E000000')
define(`REF_REGION_SIZE', `0x2020:UW') define(`REF_REGION_SIZE', `0x2020:UW')
define(`BI_SUB_MB_PART_MASK', `0x0c000000') define(`BI_SUB_MB_PART_MASK', `0x0c000000')
define(`MAX_NUM_MV', `0x00000020') define(`MAX_NUM_MV', `0x00000020')
define(`SEARCH_PATH_LEN', `0x00003F3F')
define(`INTRA_PREDICTORE_MODE', `0x11111111:UD') define(`INTRA_PREDICTORE_MODE', `0x11111111:UD')
/* GRF registers /* GRF registers
......
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