i965_drv_video/render: rendering for Sandybridge

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>

i965_drv_video/i965_defines.h

@@ -29,6 +29,10 @@
 
 #define CMD_PIPELINED_POINTERS                  CMD(3, 0, 0)
 #define CMD_BINDING_TABLE_POINTERS              CMD(3, 0, 1)
+# define GEN6_BINDING_TABLE_MODIFY_PS           (1 << 12)/* for GEN6 */
+# define GEN6_BINDING_TABLE_MODIFY_GS           (1 << 9) /* for GEN6 */
+# define GEN6_BINDING_TABLE_MODIFY_VS           (1 << 8) /* for GEN6 */
+
 #define CMD_VERTEX_BUFFERS                      CMD(3, 0, 8)
 #define CMD_VERTEX_ELEMENTS                     CMD(3, 0, 9)
 #define CMD_DRAWING_RECTANGLE                   CMD(3, 1, 0)
@@ -36,6 +40,93 @@
 #define CMD_3DPRIMITIVE                         CMD(3, 3, 0)
 
 #define CMD_DEPTH_BUFFER                        CMD(3, 1, 5)
+# define CMD_DEPTH_BUFFER_TYPE_SHIFT            29
+# define CMD_DEPTH_BUFFER_FORMAT_SHIFT          18
+
+#define CMD_CLEAR_PARAMS                        CMD(3, 1, 0x10)
+/* DW1 */
+# define CMD_CLEAR_PARAMS_DEPTH_CLEAR_VALID     (1 << 15)
+
+/* for GEN6+ */
+#define GEN6_3DSTATE_SAMPLER_STATE_POINTERS	CMD(3, 0, 0x02)
+# define GEN6_3DSTATE_SAMPLER_STATE_MODIFY_PS	(1 << 12)
+# define GEN6_3DSTATE_SAMPLER_STATE_MODIFY_GS	(1 << 9)
+# define GEN6_3DSTATE_SAMPLER_STATE_MODIFY_VS	(1 << 8)
+
+#define GEN6_3DSTATE_URB			CMD(3, 0, 0x05)
+/* DW1 */
+# define GEN6_3DSTATE_URB_VS_SIZE_SHIFT		16
+# define GEN6_3DSTATE_URB_VS_ENTRIES_SHIFT	0
+/* DW2 */
+# define GEN6_3DSTATE_URB_GS_ENTRIES_SHIFT	8
+# define GEN6_3DSTATE_URB_GS_SIZE_SHIFT		0
+
+#define GEN6_3DSTATE_VIEWPORT_STATE_POINTERS	CMD(3, 0, 0x0d)
+# define GEN6_3DSTATE_VIEWPORT_STATE_MODIFY_CC		(1 << 12)
+# define GEN6_3DSTATE_VIEWPORT_STATE_MODIFY_SF		(1 << 11)
+# define GEN6_3DSTATE_VIEWPORT_STATE_MODIFY_CLIP	(1 << 10)
+
+#define GEN6_3DSTATE_CC_STATE_POINTERS		CMD(3, 0, 0x0e)
+
+#define GEN6_3DSTATE_VS				CMD(3, 0, 0x10)
+
+#define GEN6_3DSTATE_GS				CMD(3, 0, 0x11)
+/* DW4 */
+# define GEN6_3DSTATE_GS_DISPATCH_START_GRF_SHIFT	0
+
+#define GEN6_3DSTATE_CLIP			CMD(3, 0, 0x12)
+
+#define GEN6_3DSTATE_SF				CMD(3, 0, 0x13)
+/* DW1 */
+# define GEN6_3DSTATE_SF_NUM_OUTPUTS_SHIFT		22
+# define GEN6_3DSTATE_SF_URB_ENTRY_READ_LENGTH_SHIFT	11
+# define GEN6_3DSTATE_SF_URB_ENTRY_READ_OFFSET_SHIFT	4
+/* DW2 */
+/* DW3 */
+# define GEN6_3DSTATE_SF_CULL_BOTH			(0 << 29)
+# define GEN6_3DSTATE_SF_CULL_NONE			(1 << 29)
+# define GEN6_3DSTATE_SF_CULL_FRONT			(2 << 29)
+# define GEN6_3DSTATE_SF_CULL_BACK			(3 << 29)
+/* DW4 */
+# define GEN6_3DSTATE_SF_TRI_PROVOKE_SHIFT		29
+# define GEN6_3DSTATE_SF_LINE_PROVOKE_SHIFT		27
+# define GEN6_3DSTATE_SF_TRIFAN_PROVOKE_SHIFT		25
+
+
+#define GEN6_3DSTATE_WM				CMD(3, 0, 0x14)
+/* DW2 */
+# define GEN6_3DSTATE_WM_SAMPLER_COUNT_SHITF			27
+# define GEN6_3DSTATE_WM_BINDING_TABLE_ENTRY_COUNT_SHIFT	18
+/* DW4 */
+# define GEN6_3DSTATE_WM_DISPATCH_START_GRF_0_SHIFT		16
+/* DW5 */
+# define GEN6_3DSTATE_WM_MAX_THREADS_SHIFT			25
+# define GEN6_3DSTATE_WM_DISPATCH_ENABLE			(1 << 19)
+# define GEN6_3DSTATE_WM_16_DISPATCH_ENABLE			(1 << 1)
+# define GEN6_3DSTATE_WM_8_DISPATCH_ENABLE			(1 << 0)
+/* DW6 */
+# define GEN6_3DSTATE_WM_NUM_SF_OUTPUTS_SHIFT			20
+# define GEN6_3DSTATE_WM_NONPERSPECTIVE_SAMPLE_BARYCENTRIC	(1 << 15)
+# define GEN6_3DSTATE_WM_NONPERSPECTIVE_CENTROID_BARYCENTRIC	(1 << 14)
+# define GEN6_3DSTATE_WM_NONPERSPECTIVE_PIXEL_BARYCENTRIC	(1 << 13)
+# define GEN6_3DSTATE_WM_PERSPECTIVE_SAMPLE_BARYCENTRIC		(1 << 12)
+# define GEN6_3DSTATE_WM_PERSPECTIVE_CENTROID_BARYCENTRIC	(1 << 11)
+# define GEN6_3DSTATE_WM_PERSPECTIVE_PIXEL_BARYCENTRIC		(1 << 10)
+
+
+#define GEN6_3DSTATE_CONSTANT_VS		CMD(3, 0, 0x15)
+#define GEN6_3DSTATE_CONSTANT_GS          	CMD(3, 0, 0x16)
+#define GEN6_3DSTATE_CONSTANT_PS          	CMD(3, 0, 0x17)
+
+#define GEN6_3DSTATE_SAMPLE_MASK		CMD(3, 0, 0x18)
+
+#define GEN6_3DSTATE_MULTISAMPLE		CMD(3, 1, 0x0d)
+/* DW1 */
+# define GEN6_3DSTATE_MULTISAMPLE_PIXEL_LOCATION_CENTER         (0 << 4)
+# define GEN6_3DSTATE_MULTISAMPLE_PIXEL_LOCATION_UPPER_LEFT     (1 << 4)
+# define GEN6_3DSTATE_MULTISAMPLE_NUMSAMPLES_1                  (0 << 1)
+# define GEN6_3DSTATE_MULTISAMPLE_NUMSAMPLES_4                  (2 << 1)
+# define GEN6_3DSTATE_MULTISAMPLE_NUMSAMPLES_8                  (3 << 1)
 
 #define MFX(pipeline, op, sub_opa, sub_opb)     \
     (3 << 29 |                                  \
@@ -315,7 +406,9 @@
 #define I965_VFCOMPONENT_STORE_PID    7
 
 #define VE0_VERTEX_BUFFER_INDEX_SHIFT	27
+#define GEN6_VE0_VERTEX_BUFFER_INDEX_SHIFT      26 /* for GEN6 */
 #define VE0_VALID			(1 << 26)
+#define GEN6_VE0_VALID                  (1 << 25) /* for GEN6 */
 #define VE0_FORMAT_SHIFT		16
 #define VE0_OFFSET_SHIFT		0
 #define VE1_VFCOMPONENT_0_SHIFT		28
@@ -325,8 +418,11 @@
 #define VE1_DESTINATION_ELEMENT_OFFSET_SHIFT	0
 
 #define VB0_BUFFER_INDEX_SHIFT          27
+#define GEN6_VB0_BUFFER_INDEX_SHIFT     26
 #define VB0_VERTEXDATA                  (0 << 26)
 #define VB0_INSTANCEDATA                (1 << 26)
+#define GEN6_VB0_VERTEXDATA             (0 << 20)
+#define GEN6_VB0_INSTANCEDATA           (1 << 20)
 #define VB0_BUFFER_PITCH_SHIFT          0
 
 #define _3DPRIMITIVE_VERTEX_SEQUENTIAL  (0 << 15)

i965_drv_video/i965_drv_video.c

@@ -1762,15 +1762,15 @@ i965_PutSurface(VADriverContextP ctx,
     if (flags & (VA_BOTTOM_FIELD | VA_TOP_FIELD))
         pp_flag |= I965_PP_FLAG_DEINTERLACING;
 
-    i965_render_put_surface(ctx, surface,
+    intel_render_put_surface(ctx, surface,
                             srcx, srcy, srcw, srch,
                             destx, desty, destw, desth,
                             pp_flag);
 
     if(obj_surface->subpic != VA_INVALID_ID) {	
-	i965_render_put_subpic(ctx, surface,
-                               srcx, srcy, srcw, srch,
-                               destx, desty, destw, desth);
+	intel_render_put_subpicture(ctx, surface,
+                                    srcx, srcy, srcw, srch,
+                                    destx, desty, destw, desth);
     } 
 
     dri_swap_buffer(ctx, dri_drawable);

i965_drv_video/i965_render.h

@@ -57,6 +57,8 @@ struct i965_render_state
     struct {
         dri_bo *state;
         dri_bo *viewport;
+        dri_bo *blend;
+        dri_bo *depth_stencil;
     } cc;
 
     struct {
@@ -73,7 +75,7 @@ struct i965_render_state
 
 Bool i965_render_init(VADriverContextP ctx);
 Bool i965_render_terminate(VADriverContextP ctx);
-void i965_render_put_surface(VADriverContextP ctx,
+void intel_render_put_surface(VADriverContextP ctx,
                              VASurfaceID surface,
                              short srcx,
                              short srcy,
@@ -87,7 +89,7 @@ void i965_render_put_surface(VADriverContextP ctx,
 
 
 void
-i965_render_put_subpic(VADriverContextP ctx,
+intel_render_put_subpicture(VADriverContextP ctx,
                         VASurfaceID surface,
                         short srcx,
                         short srcy,

i965_drv_video/i965_structs.h

@@ -964,4 +964,105 @@ struct i965_sampler_dndi
     } dw7;
 };
 
+
+struct gen6_blend_state
+{
+    struct {
+        unsigned int dest_blend_factor:5;
+        unsigned int source_blend_factor:5;
+        unsigned int pad3:1;
+        unsigned int blend_func:3;
+        unsigned int pad2:1;
+        unsigned int ia_dest_blend_factor:5;
+        unsigned int ia_source_blend_factor:5;
+        unsigned int pad1:1;
+        unsigned int ia_blend_func:3;
+        unsigned int pad0:1;
+        unsigned int ia_blend_enable:1;
+        unsigned int blend_enable:1;
+    } blend0;
+
+    struct {
+        unsigned int post_blend_clamp_enable:1;
+        unsigned int pre_blend_clamp_enable:1;
+        unsigned int clamp_range:2;
+        unsigned int pad0:4;
+        unsigned int x_dither_offset:2;
+        unsigned int y_dither_offset:2;
+        unsigned int dither_enable:1;
+        unsigned int alpha_test_func:3;
+        unsigned int alpha_test_enable:1;
+        unsigned int pad1:1;
+        unsigned int logic_op_func:4;
+        unsigned int logic_op_enable:1;
+        unsigned int pad2:1;
+        unsigned int write_disable_b:1;
+        unsigned int write_disable_g:1;
+        unsigned int write_disable_r:1;
+        unsigned int write_disable_a:1;
+        unsigned int pad3:1;
+        unsigned int alpha_to_coverage_dither:1;
+        unsigned int alpha_to_one:1;
+        unsigned int alpha_to_coverage:1;
+    } blend1;
+};
+
+struct gen6_color_calc_state
+{
+    struct {
+        unsigned int alpha_test_format:1;
+        unsigned int pad0:14;
+        unsigned int round_disable:1;
+        unsigned int bf_stencil_ref:8;
+        unsigned int stencil_ref:8;
+    } cc0;
+
+    union {
+        float alpha_ref_f;
+        struct {
+            unsigned int ui:8;
+            unsigned int pad0:24;
+        } alpha_ref_fi;
+    } cc1;
+
+    float constant_r;
+    float constant_g;
+    float constant_b;
+    float constant_a;
+};
+
+struct gen6_depth_stencil_state
+{
+    struct {
+        unsigned int pad0:3;
+        unsigned int bf_stencil_pass_depth_pass_op:3;
+        unsigned int bf_stencil_pass_depth_fail_op:3;
+        unsigned int bf_stencil_fail_op:3;
+        unsigned int bf_stencil_func:3;
+        unsigned int bf_stencil_enable:1;
+        unsigned int pad1:2;
+        unsigned int stencil_write_enable:1;
+        unsigned int stencil_pass_depth_pass_op:3;
+        unsigned int stencil_pass_depth_fail_op:3;
+        unsigned int stencil_fail_op:3;
+        unsigned int stencil_func:3;
+        unsigned int stencil_enable:1;
+    } ds0;
+
+    struct {
+        unsigned int bf_stencil_write_mask:8;
+        unsigned int bf_stencil_test_mask:8;
+        unsigned int stencil_write_mask:8;
+        unsigned int stencil_test_mask:8;
+    } ds1;
+
+    struct {
+        unsigned int pad0:26;
+        unsigned int depth_write_enable:1;
+        unsigned int depth_test_func:3;
+        unsigned int pad1:1;
+        unsigned int depth_test_enable:1;
+    } ds2;
+};
+
 #endif /* _I965_STRUCTS_H_ */