- 10 Sep, 2009 40 commits
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Andre Przywara authored
Signed-off-by:
Andre Przywara <andre.przywara@amd.com> Signed-off-by:
Avi Kivity <avi@redhat.com>
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Beth Kon authored
When kvm is in hpet_legacy_mode, the hpet is providing the timer interrupt and the pit should not be. So in legacy mode, the pit timer is destroyed, but the *state* of the pit is maintained. So if kvm or the guest tries to modify the state of the pit, this modification is accepted, *except* that the timer isn't actually started. When we exit hpet_legacy_mode, the current state of the pit (which is up to date since we've been accepting modifications) is used to restart the pit timer. The saved_mode code in kvm_pit_load_count temporarily changes mode to 0xff in order to destroy the timer, but then restores the actual value, again maintaining "current" state of the pit for possible later reenablement. [avi: add some reserved storage in the ioctl; make SET_PIT2 IOW] [marcelo: fix memory corruption due to reserved storage] Signed-off-by:
Beth Kon <eak@us.ibm.com> Signed-off-by:
Marcelo Tosatti <mtosatti@redhat.com> Signed-off-by:
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Gleb Natapov authored
We emulate x2apic in software, so host support is not required. Signed-off-by:
Gleb Natapov <gleb@redhat.com> Signed-off-by:
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Gleb Natapov authored
This will save a couple of IPIs. Signed-off-by:
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Gleb Natapov authored
Add tracepoint in msi/ioapic/pic set_irq() functions, in IPI sending and in the point where IRQ is placed into apic's IRR. Signed-off-by:
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Michael S. Tsirkin authored
Irqfd sets level for interrupt to 1 and then to 0. For MSI, check level so that a single message is sent. Signed-off-by:
Michael S. Tsirkin <mst@redhat.com> Signed-off-by:
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Andre Przywara authored
Some Windows versions check whether the BIOS has setup MMI/O for config space accesses on AMD Fam10h CPUs, we say "no" by returning 0 on reads and only allow disabling of MMI/O CfgSpace setup by igoring "0" writes. Signed-off-by:
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Avi Kivity authored
Create, sync, unsync, zap. Signed-off-by: -
Avi Kivity authored
Document the basic API corresponding to the 2.6.22 release. Signed-off-by: -
Avi Kivity authored
Signed-off-by: -
Jan Kiszka authored
This reverts commit 6c20e1442bb1c62914bb85b7f4a38973d2a423ba. To my understanding, it became obsolete with the advent of the more robust check in mmu_alloc_roots (89da4ff17f). Moreover, it prevents the conceptually safe pattern 1. set sregs 2. register mem-slots 3. run vcpu by setting a sticky triple fault during step 1. Signed-off-by:
Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by:
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Andre Przywara authored
Windows 7 tries to update the CPU's microcode on some processors, so we ignore the MSR write here. The patchlevel register is already handled (returning 0), because the MSR number is the same as Intel's. Signed-off-by:
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Sheng Yang authored
Some in-famous OS do unaligned writing for APIC MMIO, and the return value has been missed in recent change, then the OS hangs. Signed-off-by:
Sheng Yang <sheng@linux.intel.com> Signed-off-by:
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Gleb Natapov authored
Cosmetic only. No logic is changed by this patch. Signed-off-by:
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Gleb Natapov authored
This patch implements MSR interface to local apic as defines by x2apic Intel specification. Signed-off-by:
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Gleb Natapov authored
Directed EOI is specified by x2APIC, but is available even when lapic is in xAPIC mode. Signed-off-by:
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Avi Kivity authored
Signed-off-by: -
Avi Kivity authored
Signed-off-by: -
Andre Przywara authored
Linux guests will try to enable access to the extended PCI config space via the I/O ports 0xCF8/0xCFC on AMD Fam10h CPU. Since we (currently?) don't use ECS, simply ignore write and read attempts. Signed-off-by:
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Avi Kivity authored
Signed-off-by: -
Jiri Slaby authored
There is a missing unlock on one fail path in ioapic_mmio_write, fix that. Signed-off-by:
Jiri Slaby <jirislaby@gmail.com> Signed-off-by:
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Michael S. Tsirkin authored
Document kvm->lock nesting within kvm->slots_lock Signed-off-by:
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Michael S. Tsirkin authored
This changes bus accesses to use high-level kvm_io_bus_read/kvm_io_bus_write functions. in_range now becomes unused so it is removed from device ops in favor of read/write callbacks performing range checks internally. This allows aliasing (mostly for in-kernel virtio), as well as better error handling by making it possible to pass errors up to userspace. Signed-off-by:
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Michael S. Tsirkin authored
Use slots_lock to protect device list on the bus. slots_lock is already taken for read everywhere, so we only need to take it for write when registering devices. This is in preparation to removing in_range and kvm->lock around it. Signed-off-by:
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Michael S. Tsirkin authored
switch pit creation to slots_lock. slots_lock is already taken for read everywhere, so we only need to take it for write when creating pit. This is in preparation to removing in_range and kvm->lock around it. Signed-off-by:
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Michael S. Tsirkin authored
switch coalesced mmio slots_lock. slots_lock is already taken for read everywhere, so we only need to take it for write when changing zones. This is in preparation to removing in_range and kvm->lock around it. [avi: fix build] Signed-off-by:
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Michael S. Tsirkin authored
slots_lock is taken everywhere when device ops are called. Document this as we will use this to rework locking for io. Signed-off-by:
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Marcelo Tosatti authored
Change kvm_vcpu_is_bsp to use vcpu_id instead of bsp_vcpu pointer, which is only initialized at the end of kvm_vm_ioctl_create_vcpu. Signed-off-by:
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Marcelo Tosatti authored
Return EOPNOTSUPP for KVM_TRACE_ENABLE/PAUSE/DISABLE ioctls. Signed-off-by:
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Marcelo Tosatti authored
[avi: make it build] [avi: fold trace-arch.h into trace.h] CC: Hollis Blanchard <hollisb@us.ibm.com> Signed-off-by:
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Andre Przywara authored
KVM will inject a #GP into the guest if that tries to access unhandled MSRs. This will crash many guests. Although it would be the correct way to actually handle these MSRs, we introduce a runtime switchable module param called "ignore_msrs" (defaults to 0). If this is Y, unknown MSR reads will return 0, while MSR writes are simply dropped. In both cases we print a message to dmesg to inform the user about that. You can change the behaviour at any time by saying: # echo 1 > /sys/modules/kvm/parameters/ignore_msrs Signed-off-by:
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Andre Przywara authored
If the Linux kernel detects an C1E capable AMD processor (K8 RevF and higher), it will access a certain MSR on every attempt to go to halt. Explicitly handle this read and return 0 to let KVM run a Linux guest with the native AMD host CPU propagated to the guest. Signed-off-by:
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Andre Przywara authored
Linux tries to disable the flush filter on all AMD K8 CPUs. Since KVM does not handle the needed MSR, the injected #GP will panic the Linux kernel. Ignore setting of the HWCR.FFDIS bit in this MSR to let Linux boot with an AMD K8 family guest CPU. Signed-off-by:
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Marcelo Tosatti authored
Correct missing locking in a few places in x86's vm_ioctl handling path. Signed-off-by:
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Joerg Roedel authored
[avi: fix build on non-x86] Signed-off-by:
Joerg Roedel <joerg.roedel@amd.com> Signed-off-by:
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Joerg Roedel authored
This function is required by KVM. Signed-off-by:
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Christian Borntraeger authored
Since commit 854b5338196b1175706e99d63be43a4f8d8ab607 Author: Christian Ehrhardt <ehrhardt@linux.vnet.ibm.com> KVM: s390: streamline memslot handling s390 uses the values of the memslot instead of doing everything in the arch ioctl handler of the KVM_SET_USER_MEMORY_REGION. Unfortunately we missed to set the userspace_addr of our memslot due to our s390 ifdef in __kvm_set_memory_region. Old s390 userspace launchers did not notice, since they started the guest at userspace address 0. Because of CONFIG_DEFAULT_MMAP_MIN_ADDR we now put the guest at 1M userspace, which does not work. This patch makes sure that new.userspace_addr is set on s390. This fix should go in quickly. Nevertheless, looking at the code we should clean up that ifdef in the long term. Any kernel janitors? Signed-off-by:Christian Borntraeger <borntraeger@de.ibm.com> Signed-off-by:
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Andre Przywara authored
Handle #UD intercept of the sysexit instruction in 64bit mode returning to 32bit compat mode on an AMD host. Setup the segment descriptors for CS and SS and the EIP/ESP registers according to the manual. Signed-off-by:
Christoph Egger <christoph.egger@amd.com> Signed-off-by:
Amit Shah <amit.shah@redhat.com> Signed-off-by:
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Andre Przywara authored
Handle #UD intercept of the sysenter instruction in 32bit compat mode on an AMD host. Setup the segment descriptors for CS and SS and the EIP/ESP registers according to the manual. Signed-off-by:
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Andre Przywara authored
Handle #UD intercept of the syscall instruction in 32bit compat mode on an Intel host. Setup the segment descriptors for CS and SS and the EIP/ESP registers according to the manual. Save the RIP and EFLAGS to the correct registers. [avi: fix build on i386 due to missing R11] Signed-off-by:
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