1. 31 Jan, 2008 6 commits
    • Catalin Marinas's avatar
      ARMv7: Add Advanced SIMD (NEON) extension support · f62163c5
      Catalin Marinas authored
      This patch enables the use of the Advanced SIMD (NEON) extension on
      ARMv7. The NEON technology is a 64/128-bit hybrid SIMD architecture
      for accelerating the performance of multimedia and signal processing
      applications. The extension shares the registers with the VFP unit and
      enabling/disabling and saving/restoring follow the same rules. In
      addition, there are instructions that do not have the appropriate CP
      number encoded, the checks being made in the call_fpe function.
      Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
      f62163c5
    • Catalin Marinas's avatar
      ARMv7: Add VFPv3 support · 0b908b16
      Catalin Marinas authored
      This patch adds the support for VFPv3 (the kernel currently supports
      VFPv2). The main difference is 32 double registers (compared to 16).
      Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
      0b908b16
    • Catalin Marinas's avatar
      Add support for the common VFP subarchitecture · 8573b061
      Catalin Marinas authored
      This patch allows the VFP support code to run correctly on CPUs
      compatible with the common VFP subarchitecture specification (Appendix
      B in the ARM ARM v7-A and v7-R edition). It implements support for VFP
      subarchitecture 2 while being backwards compatible with
      subarchitecture 1.
      
      On VFP subarchitecture 1, the arithmetic exceptions are asynchronous
      (or imprecise as described in the old ARM ARM) unless the FPSCR.IXE
      bit is 1. The exceptional instructions can be read from FPINST and
      FPINST2 registers. With VFP subarchitecture 2, the arithmetic
      exceptions can also be synchronous and marked by the FPEXC.DEX bit
      (the FPEXC.EX bit is cleared). CPUs implementing the synchronous
      arithmetic exceptions don't have the FPINST and FPINST2 registers and
      accessing them would trigger and undefined exception.
      
      Note that FPEXC.EX bit has an additional meaning on subarchitecture 1
      - if it isn't set, there is no additional information in FPINST and
      FPINST2 that needs to be saved at context switch or when lazy-loading
      the VFP state of a different thread.
      
      The patch also removes the clearing of the cumulative exception flags in
      FPSCR when additional exceptions were raised. It is up to the user
      application to clear these bits.
      Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
      8573b061
    • Catalin Marinas's avatar
      Add a printascii call in the vprintk function · a2e8e76a
      Catalin Marinas authored
      This is useful for initial debugging and when CONFIG_DEBUG_LL is set.
      Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
      a2e8e76a
    • Catalin Marinas's avatar
      run_init_process() error reporting · 03668264
      Catalin Marinas authored
      This function prints the error code returned by execve.
      Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
      03668264
    • Catalin Marinas's avatar
      Cross-compilation definitions for ARM. · c210df94
      Catalin Marinas authored
      Sets ARCH to arm and CROSS_COMPILE to arm-none-linux-gnueabi-.
      Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
      c210df94
  2. 24 Jan, 2008 32 commits
  3. 23 Jan, 2008 2 commits