1. 12 May, 2009 1 commit
    • Paul Walmsley's avatar
      OMAP3 SRAM: mark OCM RAM as Non-cacheable Normal memory · d9295746
      Paul Walmsley authored
      Mark the SRAM (aka OCM RAM) as Non-cacheable Normal memory[1].  This
      is to prevent the ARM from evicting existing cache lines to SDRAM
      while code is executing from the SRAM.  Necessary since one of the
      primary uses for the SRAM is to hold the code and data for the CORE
      DPLL M2 divider reprogramming code, which must execute while the SDRC
      is idled.  If the ARM attempts to write cache lines back to the while
      the SRAM code is running, the ARM will stall[2].
      
      TI deals with this problem in the CDP kernel by marking the SRAM as
      Strongly-ordered memory.
      
      Tero Kristo <tero.kristo@nokia.com> caught a bug in an earlier version of
      this patch - thanks Tero.
      
      ...
      
      1. ARMv7 ARM (DDI 0406A) pp. A3-30, A3-31, B3-32.
      
      2. Private communication with Richard Woodruff <r-woodruff2@ti.com>
      Signed-off-by: default avatarPaul Walmsley <paul@pwsan.com>
      Cc: Tero Kristo <tero.kristo@nokia.com>
      Cc: Richard Woodruff <r-woodruff2@ti.com>
      d9295746
  2. 11 May, 2009 12 commits
  3. 10 May, 2009 12 commits
  4. 09 May, 2009 15 commits