- 21 Sep, 2009 1 commit
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Mark Brown authored
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
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- 19 Sep, 2009 1 commit
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jassi brar authored
New machine driver for WM8580 I2S i/f on SMDK64XX. By default SoC-Slave is set and WM8580 is configured to use it's PLLA to generate clocks from a 12MHz crystal attached to WM8580. [Added dependency on BROKEN since the IISv4 interface hasn't been merged yet, fixed the PLL API usage and removed the disabling of the PLL in the hw_free function since that'll break simultaneous playback and record -- broonie.] Signed-off-by: Jassi <jassi.brar@samsung.com> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
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- 18 Sep, 2009 4 commits
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Mark Brown authored
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Jassi authored
Instead of always returnig pointer to the 'audio-bus' clock, check which clock is used to generate internal clocks and then return it's pointer. Signed-off-by: Jassi <jassi.brar@samsung.com> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
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Chaithrika U S authored
McASP register settings are not correct for DSP mode of operation. There is a channel swap initally. This patch provides fixes to the register values for proper working. Tested on DA830/OMAP-L137 EVM, DM6467 EVM. Signed-off-by: Chaithrika U S <chaithrika@ti.com> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
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Cliff Cai authored
If the sound system hasn't been utilized yet and we suspend, then we attempt to save/restore using state that doesn't exist. So use a global handle instead to reconfigure properly. Signed-off-by: Cliff Cai <cliff.cai@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
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- 17 Sep, 2009 4 commits
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Barry Song authored
Commit dc7d7b83 trimmed the platform_device parameter from all of the suspend functions, but it also accidentally removed it from the resume function in the Blackfin I2S driver. So restore it. Signed-off-by: Barry Song <barry.song@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
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Barry Song authored
Signed-off-by: Barry Song <barry.song@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
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Mike Frysinger authored
Signed-off-by: Mike Frysinger <vapier@gentoo.org> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
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Cliff Cai authored
Somewhere along the line, most of SND_BF5XX_MULTICHAN_SUPPORT handling was merged, but two places were missed (the probe/resume functions). Restore handling of this option so it gets initialized properly. Signed-off-by: Cliff Cai <cliff.cai@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
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- 16 Sep, 2009 2 commits
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Huang Weiyi authored
Remove unused #include <linux/version.h>('s) in sound/soc/codecs/ad1836.c sound/soc/codecs/ad1938.c sound/soc/codecs/wm8974.c Signed-off-by: Huang Weiyi <weiyi.huang@gmail.com> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
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Mark Brown authored
CDCLK can either be an output generated by the CPU, intended for use as the CODEC master clock, or an input (probably from the CODEC) providing a master clock for the IIS block. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
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- 15 Sep, 2009 4 commits
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Miguel Aguilar authored
This patch enables tlv320aic3101 support on DM365 EVM and it was tested on DM365 EVM rev c. Note: this patch was created based on temp/asoc branch. Signed-off-by: Miguel Aguilar <miguel.aguilar@ridgerun.com> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
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Barry Song authored
Signed-off-by: Barry Song <barry.song@analog.com> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
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Jassi authored
1) Explicitly set LRCLK polarity for I2S Vs LSM/MSB modes. 2) Convert from numerical to bit-field values for BCLK selection. 3) Use proper error checking for return value from clk_get Signed-off-by: Jassi <jassi.brar@samsung.com> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
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Jassi authored
s3c2412_snd_lrsync() maybe reached with IRQs disabled and if LRCLK is dead due to improper initialization of CPU or CODEC, the system gets stuck in the loop because jiffies may never get updated. Implemented counter based wait mechanism for atleast the same timeout period. Signed-off-by: Jassi <jassi.brar@samsung.com> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
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- 14 Sep, 2009 1 commit
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Mark Brown authored
Also display streams all the time while we're here. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
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- 13 Sep, 2009 1 commit
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Barry Song authored
The patch adds an interface to set the relationship between audio channel number and slot number. The interface should be really useful because audio channel n doesn't always use slot n in all platforms. And for some devices, the relationship even can change with sound mode switch in 2.1,3.1,4.1,5.1,6.1,7.1 etc. Signed-off-by: Barry Song <21cnbao@gmail.com> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
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- 12 Sep, 2009 1 commit
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Julia Lawall authored
Error handling code following a kzalloc should free the allocated data. Error handling code following an ioremap should iounmap the allocated data. The semantic match that finds the first problem is as follows: (http://www.emn.fr/x-info/coccinelle/) // <smpl> @r exists@ local idexpression x; statement S; expression E; identifier f,f1,l; position p1,p2; expression *ptr != NULL; @@ x@p1 = \(kmalloc\|kzalloc\|kcalloc\)(...); ... if (x == NULL) S <... when != x when != if (...) { <+...x...+> } ( x->f1 = E | (x->f1 == NULL || ...) | f(...,x->f1,...) ) ...> ( return \(0\|<+...x...+>\|ptr\); | return@p2 ...; ) @script:python@ p1 << r.p1; p2 << r.p2; @@ print "* file: %s kmalloc %s return %s" % (p1[0].file,p1[0].line,p2[0].line) // </smpl> Signed-off-by: Julia Lawall <julia@diku.dk> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
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- 09 Sep, 2009 1 commit
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Joonyoung Shim authored
The AK4671 is a stereo CODEC with a built-in Microphone-Amplifier, Receiver-Amplifier and Headphone-Amplifier. The datasheet for the ak4671 can find at the following url: http://www.asahi-kasei.co.jp/akm/en/product/ak4671/ak4671_f01e.pdfSigned-off-by: Joonyoung Shim <jy0922.shim@samsung.com> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
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- 08 Sep, 2009 2 commits
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Mark Brown authored
Some chips with complex internal supply (particularly clocking) arragements may have multiple options for some of the supply connections. Since these don't affect user-visible audio routing the expectation would be that they would be managed automatically by one of the drivers. Support these users by allowing routes to have a connected function which is queried before the connectedness of the path is checked as normal. Currently this is only done for supplies, other widgets could be supported but are not currently since the expectation for them is that audio routing will be under the control of userspace. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
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Manuel Lauss authored
This patch fixes the following bugs: - only reprogram bitdepth if it has changed since last call to hw_params. - add locking inside ac97_read/write functions: When reprogramming sample depth, the ac97 unit has to be disabled, which should not be done in the middle of codec register accesses. - retry timed-out codec register accesses. - wait for status bits to set/clear when starting/stopping various functional blocks; very important after reenabling AC97 unit else sound may be distorted (e.g. high-pitch noise in 1kHz sine wave). - clear fifos before/after starting/stopping RX/TX. - longer timeouts waiting for PSC/AC97 ready after cold reset with certain codecs this can take ridiculous amounts of time. Run-tested on various Au1200 platforms with various codecs. Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
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- 07 Sep, 2009 3 commits
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Mark Brown authored
It's the 8th enum of a zero indexed array. This is why I don't let new drivers use these arrays of enums... Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Cc: stable@kernel.org
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Mark Brown authored
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
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Joonyoung Shim authored
This patch is for the AK4671 codec driver using this format. Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
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- 05 Sep, 2009 1 commit
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Mark Brown authored
More and more devices feature PLLs and FLLs with the ability to select between multiple input clocks. In order to better support these devices a new argument, source, has been added to the set_pll() configuration API. Using set_clkdiv() is often difficult due to the need to stop the PLL/FLL before any reconfiguration can be done. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
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- 04 Sep, 2009 1 commit
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Robert Schwebel authored
Today's linux-next fails to build with sound/arm/pxa2xx-ac97.c: In function 'pxa2xx_ac97_probe': sound/arm/pxa2xx-ac97.c:211: error: 'pxa2xx_audio_ops_t' has no member named 'codec_data' make[2]: *** [sound/arm/pxa2xx-ac97.o] Error 1 It looks like commit e2365bf3 has introduced this; patch below. Signed-off-by: Robert Schwebel <r.schwebel@pengutronix.de> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
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- 02 Sep, 2009 1 commit
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Mark Brown authored
Avoids potential issues if we read back unexpected values during a read/modify/write cycle. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
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- 01 Sep, 2009 2 commits
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jassi brar authored
Bug was caught while trying to use WM8580 as I2S master on SMDK. Symptoms were lesser LRCLK read by CRO(41.02 instead of 44.1 KHz) Solved by referring to WM8580A manual and setting mask value correctly and making the code to not touch 'reserved' bits of PLL4 register. Signed-off-by: Jassi <jassi.brar@samsung.com> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
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Barry Song authored
As discussed, the patch uses the original TDM order without rewriting. For the match between TDM slot number and audio channel number, a new API need be added. Signed-off-by: Barry Song <21cnbao@gmail.com> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
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- 28 Aug, 2009 2 commits
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Jarkko Nikula authored
The McBSP1 port in OMAP3 processors (I believe OMAP2 too but I don't have specifications to check it) have additional CLKR and FSR pins for McBSP1 receiver. Reset default is that receiver is using bit clock and frame sync signal from those pins but it is possible to configure to use also CLKX and FSX pins as well. In fact, other McBSP ports are doing that internally that transmitter and receiver share the CLKX and FSX. Add functionaly that machine drivers can set the CLKR and FSR sources by using the snd_soc_dai_set_sysclk. Thanks to "Aggarwal, Anuj" <anuj.aggarwal@ti.com> for reporting the issue. Signed-off-by: Jarkko Nikula <jhnikula@gmail.com> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
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Chaithrika U S authored
Also, the codec setup data structure has to remain for successful probe. Signed-off-by: Chaithrika U S <chaithrika@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
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- 26 Aug, 2009 4 commits
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Mark Brown authored
If the requested FLL configuration is the one we're currently running in it's at best pointless to reconfigure the FLL. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
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Mark Brown authored
We now need the PCM header to kick the DMA. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
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Mark Brown authored
Now that we don't need the I2C address for the device the platform data is redundant so allow it to be omitted. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Tested-by: Chaithrika U S <chaithrika@ti.com>
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Mark Brown authored
No point in building them for S3C64xx, certainly no sense in running into build issues there. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
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- 25 Aug, 2009 4 commits
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Candelaria Villareal, Jorge authored
Fix the write to PMBR1 register through I2C. Also, the constant which holds the value to write is now called TWL4030_GPIO6_PWM0_MUTE. This name is based on TRM to avoid confusion. Signed-off-by: Jorge Eduardo Candelaria <x0107209@ti.com> Acked-by: Peter Ujfalusi <peter.ujfalusi@nokia.com> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
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Shine Liu authored
s3c24xx dma has the auto reload feature, when the the trnasfer is done, CURR_TC(DSTAT[19:0], current value of transfer count) reaches 0, and DMA ACK becomes 1, and then, TC(DCON[19:0]) will be loaded into CURR_TC. So the transmission is repeated. IRQ is issued while auto reload occurs. We change the DISRC and DCON[19:0] in the ISR, but at this time, the auto reload has been performed already. The first block is being re-transmitted by the DMA. So we need rewrite the DISRC and DCON[19:0] for the next block immediatly after the this block has been started to be transported. The function s3c2410_dma_started() is for this perpose, which is called in the form of "s3c2410_dma_ctrl(prtd->params->channel, S3C2410_DMAOP_STARTED);" in s3c24xx_pcm_trigger(). But it is not correct. DMA transmission won't start until DMA REQ signal arrived, it is the time s3c24xx_snd_txctrl(1) or s3c24xx_snd_rxctrl(1) is called in s3c24xx_i2s_trigger(). In the current framework, s3c24xx_pcm_trigger() is always called before s3c24xx_pcm_trigger(). So the s3c2410_dma_started() should be called in s3c24xx_pcm_trigger() after s3c24xx_snd_txctrl(1) or s3c24xx_snd_rxctrl(1) is called in this function. However, s3c2410_dma_started() is dma related, to call this function we should provide the channel number, which is given by substream->runtime->private_data->params->channel. The private_data points to a struct s3c24xx_runtime_data object, which is define in s3c24xx_pcm.c, so s3c2410_dma_started() can't be called in s3c24xx_i2s.c Fix this by moving the call to signal the DMA started to the DAI drivers. Signed-off-by: Shine Liu <liuxian@redflag-linux.com> Signed-off-by: Shine Liu <shinel@foxmail.com> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
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Jarkko Nikula authored
Functionality of functions omap_mcbsp_xmit_enable and omap_mcbsp_recv_enable can be merged into omap_mcbsp_start and omap_mcbsp_stop since API of those omap_mcbsp_start and omap_mcbsp_stop was changed recently allowing to start and stop individually the transmitter and receiver. This cleans up the code in arch/arm/plat-omap/mcbsp.c and in sound/soc/omap/omap-mcbsp.c which was the only user for those removed functions. Signed-off-by: Jarkko Nikula <jhnikula@gmail.com> Acked-by: Eero Nurkkala <ext-eero.nurkkala@nokia.com> Cc: Peter Ujfalusi <peter.ujfalusi@nokia.com> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
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Jarkko Nikula authored
Commit ca6e2ce0 is setting up few XCCR and RCCR bits for I2S and DPS_A formats. Part of the bits are already set for all formats and I believe that XDISABLE and RDISABLE bits are format independent. As XCCR and RCCR are found only from OMAP2430 and OMAP34xx, I move setup of XDISABLE and RDISABLE to where those cpu's are tested and remove format dependent part for simplicity. Signed-off-by: Jarkko Nikula <jhnikula@gmail.com> Acked-by: Eero Nurkkala <ext-eero.nurkkala@nokia.com> Cc: Peter Ujfalusi <peter.ujfalusi@nokia.com> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
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