- 22 Jul, 2007 40 commits
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Andy Whitcroft authored
We are seeing corruption of the decompressed kernel. It is suspected that this is platform specific as it has yet to be seen on any other x86. Move the kernel to the 16MB boundary. Signed-off-by:
Andy Whitcroft <apw@shadowen.org> Signed-off-by:
Andrew Morton <akpm@linux-foundation.org> Signed-off-by:
Andi Kleen <ak@suse.de> Signed-off-by:
Linus Torvalds <torvalds@linux-foundation.org>
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Jesper Juhl authored
Remove unneeded test of task != NULL from arch/i386/kernel/traps.c::dump_trace() At the start of the function we have this test: if (!task) task = current; so further down there's no need to test 'task'. Signed-off-by:Jesper Juhl <jesper.juhl@gmail.com> Signed-off-by:
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William Lee Irwin III authored
PAE is useful for more than supporting more than 4GB RAM. It supports expanded swapspace and NX executable protections. Some users may want NX or expanded swapspace support without the overhead or instability of highmem. For these reasons, the following patch divorces CONFIG_X86_PAE from CONFIG_HIGHMEM64G. Cc: Mark Lord <lkml@rtr.ca> Signed-off-by:
William Irwin <wli@holomorphy.com> Signed-off-by:
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Thomas Gleixner authored
Some systems have a HPET which is not incrementing, which leads to a complete hang. Detect it during HPET setup. Signed-off-by:
Thomas Gleixner <tglx@linutronix.de> Cc: john stultz <johnstul@us.ibm.com> Cc: <stable@kernel.org> Signed-off-by:
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James Jarvis authored
The following patch enables reboot through BIOS on the Dell Optiplex 745 Small Form Factor base, on which reboot hangs. The larger form factor does not require this, hence the match on DMI_BOARD_NAME. Signed-off-by:
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Rafael J. Wysocki authored
On some systems the ACPI NVS area is located in the first 1 MB of RAM and it is overwritten by the i386 code during the restore after hibernation. This confuses the ACPI platform firmware that doesn't update the AC adapter status appropriately as a result (http://bugzilla.kernel.org/show_bug.cgi?id=7995). The solution is to register the reserved memory in the first 1 MB as 'nosave', so that swsusp doesn't touch it during the restore. Also, this has been done on x86_64 for a long time now, so this patch makes the i386 restore code behave like the x86_64 one. [akpm@linux-foundation.org: build fix] Signed-off-by:
Rafael J. Wysocki <rjw@sisk.pl> Acked-by:
Pavel Machek <pavel@ucw.cz> Cc: David Rientjes <rientjes@google.com> Signed-off-by:
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Sam Ravnborg authored
Fix following warning: WARNING: arch/i386/kernel/built-in.o(.init.text+0x3818): Section mismatch: reference to .exit.text:cache_remove_dev (between 'cacheinfo_cpu_callback' and 'cache_sysfs_init') It points out that a function marked __cpuexit is calling a function marked __cpuinit => oops. The call happens only in an error-condition which may explain why we have not seen it before. The offending function was not used anywhere else - so marked it __cpuexit. Note: This warning triggers only with a local copy of modpost but that version will soon be pushed out. Signed-off-by:Sam Ravnborg <sam@ravnborg.org> Signed-off-by:
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Adrian Bunk authored
pgd_{c,d}tor() can now become static. Signed-off-by:Adrian Bunk <bunk@stusta.de> Signed-off-by:
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Muli Ben-Yehuda authored
After the bitmap changes we can get rid of the unlocked versions of calgary_unmap_sg and iommu_free. Fold __calgary_unmap_sg and __iommu_free into their calgary_unmap_sg and iommu_free, respectively. Signed-off-by:
Muli Ben-Yehuda <muli@il.ibm.com> Signed-off-by:
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Yinghai Lu authored
there function are called via dma_ops->.., so change them to static Signed-off-by:
Yinghai Lu <yinghai.lu@sun.com> Signed-off-by:
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Muli Ben-Yehuda authored
Currently the IOMMU table's lock protects both the bitmap and access to the hardware's TCE table. Access to the TCE table is synchronized through the bitmap; therefore, only hold the lock while modifying the bitmap. This gives a yummy 10-15% reduction in CPU utilization for netperf on a large SMP machine. Signed-off-by:
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Muli Ben-Yehuda authored
No actual code was harmed in the production of this patch. Thanks to Andrew Morton <akpm@linux-foundation.org> for telling me about checkpatch.pl. Signed-off-by:
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Muli Ben-Yehuda authored
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Muli Ben-Yehuda authored
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Muli Ben-Yehuda authored
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Guillaume Thouvenin authored
Cleanup unneeded macros used for register space address calculation. Now we are using the EBDA to find the space address. Signed-off-by:
Guillaume Thouvenin <guillaume.thouvenin@bull.net> Signed-off-by:
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Muli Ben-Yehuda authored
This works around a bug where DMAs that have the same addresses as some MEM regions do not go through. Not clear yet if this is due to a mis-configuration or something deeper. [akpm@linux-foundation.org: coding style fixlet] Signed-off-by:
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Muli Ben-Yehuda authored
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Muli Ben-Yehuda authored
Provide seperate versions for Calgary and CalIOC2 Also print out the PCIe Root Complex Status on CalIOC2 errors Signed-off-by:
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Muli Ben-Yehuda authored
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Muli Ben-Yehuda authored
[akpm@linux-foundation.org>: make calioc2_chip_ops static] Signed-off-by:
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Muli Ben-Yehuda authored
CalIOC2 is a PCI-e implementation of the Calgary logic. Most of the programming details are the same, but some differ, e.g., TCE cache flush. This patch introduces CalIOC2 support - detection and various support routines. It's not expected to work yet (but will with follow-on patches). Signed-off-by:
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Muli Ben-Yehuda authored
... in preparation for doing it differently for CalIOC2. Signed-off-by:
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Muli Ben-Yehuda authored
Calgary and CalIOC2 share most of the same logic. Introduce struct cal_chipset_ops for quirks and tce flush logic which are [akpm@linux-foundation.org: make calgary_chip_ops static] Signed-off-by:
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Muli Ben-Yehuda authored
Move the aic94xx split completion timeout handling there. Signed-off-by:
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Muli Ben-Yehuda authored
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Muli Ben-Yehuda authored
... will be used by CalIOC2 later Signed-off-by:
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Adrian Bunk authored
The Rise CPUs were only very short-lived, and there are no reports of anyone both owning one and running Linux on it. Googling for the printk string "CPU: Rise iDragon" didn't find any dmesg available online. If it turns out that against all expectations there are actually users reverting this patch would be easy. This patch will make the kernel images smaller by a few bytes for all i386 users. Signed-off-by:
Dave Jones <davej@redhat.com> Signed-off-by:
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Eric W. Biederman authored
On x86_64 kernel, level triggered irq migration gets initiated in the context of that interrupt(after executing the irq handler) and following steps are followed to do the irq migration. 1. mask IOAPIC RTE entry; // write to IOAPIC RTE 2. EOI; // processor EOI write 3. reprogram IOAPIC RTE entry // write to IOAPIC RTE with new destination and // and interrupt vector due to per cpu vector // allocation. 4. unmask IOAPIC RTE entry; // write to IOAPIC RTE Because of the per cpu vector allocation in x86_64 kernels, when the irq migrates to a different cpu, new vector(corresponding to the new cpu) will get allocated. An EOI write to local APIC has a side effect of generating an EOI write for level trigger interrupts (normally this is a broadcast to all IOAPICs). The EOI broadcast generated as a side effect of EOI write to processor may be delayed while the other IOAPIC writes (step 3 and 4) can go through. Normally, the EOI generated by local APIC for level trigger interrupt contains vector number. The IOAPIC will take this vector number and search the IOAPIC RTE entries for an entry with matching vector number and clear the remote IRR bit (indicate EOI). However, if the vector number is changed (as in step 3) the IOAPIC will not find the RTE entry when the EOI is received later. This will cause the remote IRR to get stuck causing the interrupt hang (no more interrupt from this RTE). Current x86_64 kernel assumes that remote IRR bit is cleared by the time IOAPIC RTE is reprogrammed. Fix this assumption by checking for remote IRR bit and if it still set, delay the irq migration to the next interrupt arrival event(hopefully, next time remote IRR bit will get cleared before the IOAPIC RTE is reprogrammed). Initial analysis and patch from Nanhai. Clean up patch from Suresh. Rewritten to be less intrusive, and to contain a big fat comment by Eric. [akpm@linux-foundation.org: fix comments] Acked-by:Ingo Molnar <mingo@elte.hu> Cc: Nanhai Zou <nanhai.zou@intel.com> Acked-by:
Suresh Siddha <suresh.b.siddha@intel.com> Cc: Asit Mallick <asit.k.mallick@intel.com> Cc: Keith Packard <keith.packard@intel.com> Signed-off-by:
Eric W. Biederman <ebiederm@xmission.com> Signed-off-by:
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Venki Pallipadi authored
This helps to reduce the frequency at which the CPU must be taken out of a lower-power state. Signed-off-by:
Venkatesh Pallipadi <venkatesh.pallipadi@intel.com> Acked-by:
Tim Hockin <thockin@hockin.org> Signed-off-by:
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Andrew Morton authored
Prevent stuff like this: mm/vmalloc.c: In function 'unmap_kernel_range': mm/vmalloc.c:75: warning: unused variable 'start' Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by:
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Alan Stern authored
This patch (as921) adds code to the show_regs() routine in i386 and x86_64 to print the contents of the debug registers along with all the others. Signed-off-by:
Alan Stern <stern@rowland.harvard.edu> Signed-off-by:
Roland McGrath <roland@redhat.com> Signed-off-by:
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Nigel Cunningham authored
Signed-off-by:
Nigel Cunningham <nigel@nigel.suspend2.net> Cc: Randy Dunlap <rdunlap@xenotime.net> Cc: "Rafael J. Wysocki" <rjw@sisk.pl> Cc: Pavel Machek <pavel@ucw.cz> Acked-by:
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Sam Ravnborg authored
Following section mismatch warnings were reported by Andrey Borzenkov: WARNING: arch/i386/kernel/built-in.o - Section mismatch: reference to .init.text:amd_init_mtrr from .text between 'mtrr_bp_init' (at offset 0x967a) and 'mtrr_attrib_to_str' WARNING: arch/i386/kernel/built-in.o - Section mismatch: reference to .init.text:cyrix_init_mtrr from .text between 'mtrr_bp_init' (at offset 0x967f) and 'mtrr_attrib_to_str' WARNING: arch/i386/kernel/built-in.o - Section mismatch: reference to .init.text:centaur_init_mtrr from .text between 'mtrr_bp_init' (at offset 0x9684) and 'mtrr_attrib_to_str' WARNING: arch/i386/kernel/built-in.o - Section mismatch: reference to .init.text: from .text between 'get_mtrr_state' (at offset 0xa735) and 'generic_get_mtrr' WARNING: arch/i386/kernel/built-in.o - Section mismatch: reference to .init.text: from .text between 'get_mtrr_state' (at offset 0xa749) and 'generic_get_mtrr' WARNING: arch/i386/kernel/built-in.o - Section mismatch: reference to .init.text: from .text between 'get_mtrr_state' (at offset 0xa770) and 'generic_get_mtrr' It was tracked down to a few functions missing __init tag. Compile tested only. Signed-off-by:
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Truxton Fulton authored
Commit 59f4e7d5 fixed machine rebooting on Truxton's machine (when no keyboard was present). But it broke it on Lee's machine. The patch reinstates the old (pre-59f4e7d5) code and if that doesn't work out, try the new, post-59f4e7d5 code instead. Cc: Lee Garrett <lee-in-berlin@web.de> Signed-off-by:
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Tim Hockin authored
Background: The MCE handler has several paths that it can take, depending on various conditions of the MCE status and the value of the 'tolerant' knob. The exact semantics are not well defined and the code is a bit twisty. Description: This patch makes the MCE handler's behavior more clear by documenting the behavior for various 'tolerant' levels. It also fixes or enhances several small things in the handler. Specifically: * If RIPV is set it is not safe to restart, so set the 'no way out' flag rather than the 'kill it' flag. * Don't panic() on correctable MCEs. * If the _OVER bit is set *and* the _UC bit is set (meaning possibly dropped uncorrected errors), set the 'no way out' flag. * Use EIPV for testing whether an app can be killed (SIGBUS) rather than RIPV. According to docs, EIPV indicates that the error is related to the IP, while RIPV simply means the IP is valid to restart from. * Don't clear the MCi_STATUS registers until after the panic() path. This leaves the status bits set after the panic() so clever BIOSes can find them (and dumb BIOSes can do nothing). This patch also calls nonseekable_open() in mce_open (as suggested by akpm). Result: Tolerant levels behave almost identically to how they always have, but not it's well defined. There's a slightly higher chance of panic()ing when multiple errors happen (a good thing, IMHO). If you take an MBE and panic(), the error status bits are not cleared. Alternatives: None. Testing: I used software to inject correctable and uncorrectable errors. With tolerant = 3, the system usually survives. With tolerant = 2, the system usually panic()s (PCC) but not always. With tolerant = 1, the system always panic()s. When the system panic()s, the BIOS is able to detect that the cause of death was an MC4. I was not able to reproduce the case of a non-PCC error in userspace, with EIPV, with (tolerant < 3). That will be rare at best. Signed-off-by:Tim Hockin <thockin@google.com> Signed-off-by:
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Tim Hockin authored
Background: /dev/mcelog is typically polled manually. This is less than optimal for situations where accurate accounting of MCEs is important. Calling poll() on /dev/mcelog does not work. Description: This patch adds support for poll() to /dev/mcelog. This results in immediate wakeup of user apps whenever the poller finds MCEs. Because the exception handler can not take any locks, it can not call the wakeup itself. Instead, it uses a thread_info flag (TIF_MCE_NOTIFY) which is caught at the next return from interrupt or exit from idle, calling the mce_user_notify() routine. This patch also disables the "fake panic" path of the mce_panic(), because it results in printk()s in the exception handler and crashy systems. This patch also does some small cleanup for essentially unused variables, and moves the user notification into the body of the poller, so it is only called once per poll, rather than once per CPU. Result: Applications can now poll() on /dev/mcelog. When an error is logged (whether through the poller or through an exception) the applications are woken up promptly. This should not affect any previous behaviors. If no MCEs are being logged, there is no overhead. Alternatives: I considered simply supporting poll() through the poller and not using TIF_MCE_NOTIFY at all. However, the time between an uncorrectable error happening and the user application being notified is *the*most* critical window for us. Many uncorrectable errors can be logged to the network if given a chance. I also considered doing the MCE poll directly from the idle notifier, but decided that was overkill. Testing: I used an error-injecting DIMM to create lots of correctable DRAM errors and verified that my user app is woken up in sync with the polling interval. I also used the northbridge to inject uncorrectable ECC errors, and verified (printk() to the rescue) that the notify routine is called and the user app does wake up. I built with PREEMPT on and off, and verified that my machine survives MCEs. [wli@holomorphy.com: build fix] Signed-off-by:
William Irwin <bill.irwin@oracle.com> Signed-off-by:
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Tim Hockin authored
Background: /dev/mcelog is a clear-on-read interface. It is currently possible for multiple users to open and read() the device. Users are protected from each other during any one read, but not across reads. Description: This patch adds support for O_EXCL to /dev/mcelog. If a user opens the device with O_EXCL, no other user may open the device (EBUSY). Likewise, any user that tries to open the device with O_EXCL while another user has the device will fail (EBUSY). Result: Applications can get exclusive access to /dev/mcelog. Applications that do not care will be unchanged. Alternatives: A simpler choice would be to only allow one open() at all, regardless of O_EXCL. Testing: I wrote an application that opens /dev/mcelog with O_EXCL and observed that any other app that tried to open /dev/mcelog would fail until the exclusive app had closed the device. Caveats: None. Signed-off-by:
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Aaron Durbin authored
Insert the unclaimed MMCONFIG resources into the resource tree without the IORESOURCE_BUSY flag during late initialization. This allows the MMCONFIG regions to be visible in the iomem resource tree without interfering with other system resources that were discovered during PCI initialization. [akpm@linux-foundation.org: nanofixes] Signed-off-by:
Aaron Durbin <adurbin@google.com> Cc: David Rientjes <rientjes@google.com> Signed-off-by:
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David Rientjes authored
When we are in the emulated NUMA case, we need to make sure that all existing apicid_to_node mappings that point to real node ID's now point to the equivalent fake node ID's. If we simply iterate over all apicid_to_node[] members for each node, we risk remapping an entry if it shares a node ID with a real node. Since apicid's may not be consecutive, we're forced to create an automatic array of apicid_to_node mappings and then copy it over once we have finished remapping fake to real nodes. Signed-off-by:
David Rientjes <rientjes@google.com> Signed-off-by:
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