1. 27 May, 2009 2 commits
    • Eric Anholt's avatar
      drm/i915: Apply a big hammer to 865 GEM object CPU cache flushing. · cfa16a0d
      Eric Anholt authored
      On the 865, but not the 855, the clflush we do appears to not actually make
      it out to the hardware all the time.  An easy way to safely reproduce was
      X -retro, which would show that some of the blits involved in drawing the
      lovely root weave didn't make it out to the hardware.  Those blits are 32
      bytes each, and 1-2 would be missing at various points around the screen.
      Other experimentation (doing more clflush, doing more AGP chipset flush,
      poking at some more device registers to maybe trigger more flushing) didn't
      help.  krh came up with the wbinvd as a way to successfully get all those
      blits to appear.
      Signed-off-by: default avatarEric Anholt <eric@anholt.net>
      cfa16a0d
    • Eric Anholt's avatar
      drm/i915: Fix tiling pitch handling on 8xx. · e76a16de
      Eric Anholt authored
      The pitch field is an exponent on pre-965, so we were rejecting buffers
      on 8xx that we shouldn't have.  915 got lucky in that the largest legal
      value happened to match (8KB / 512 = 0x10), but 8xx has a smaller tile width.
      Additionally, we programmed that bad value into the register on 8xx, so the
      only pitch that would work correctly was 4096 (512-1023 pixels), while others
      would probably give bad rendering or hangs.
      Signed-off-by: default avatarEric Anholt <eric@anholt.net>
      
      fd.o bug #20473.
      e76a16de
  2. 26 May, 2009 32 commits
  3. 25 May, 2009 6 commits