- 11 Dec, 2009 5 commits
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Felix Radensky authored
On MPC8572 and MPC8536 the status of GPIO pins configured as output cannot be determined by reading GPDAT register. Workaround by reading the status of input pins from GPDAT and the status of output pins from a shadow register. Signed-off-by:
Felix Radensky <felix@embedded-sol.com> Signed-off-by:
Kumar Gala <galak@kernel.crashing.org>
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Peter Korsgaard authored
gpiolib returns -ENXIO if struct gpio_chip::to_irq isn't set, so it's safe to always call. Signed-off-by:
Peter Korsgaard <jacmet@sunsite.dk> Signed-off-by:
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Anton Vorontsov authored
- Add nodes for PMC and GTM controllers. GTM4 can be used as a wakeup source; - Add fsl,magic-packet properties to eTSEC nodes, i.e. wake-on-lan support. Unlike MPC8313 processors, MPC8315 can resume from deep sleep upon magic packet reception. Signed-off-by:
Anton Vorontsov <avorontsov@ru.mvista.com> Acked-by:
Scott Wood <scottwood@freescale.com> Signed-off-by:
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Anton Vorontsov authored
We need to save SICRL, SICRH and SCCR registers on suspend, and restore them on resume. Otherwise, we lose IO and clocks setup on MPC8315E-RDB boards when ULPI USB PHY is used (non-POR setup). Signed-off-by:
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Anton Vorontsov authored
Currently 83xx PMC driver clears deep_sleeping variable very early, before devices are resumed. This makes fsl_deep_sleep() unusable in drivers' resume() callback. Sure, drivers can store fsl_deep_sleep() value on suspend and use the stored value on resume. But a better solution is to postpone clearing the deep_sleeping variable, i.e. move it into finish() callback. Signed-off-by:
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- 10 Dec, 2009 1 commit
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Mark Ware authored
Port C interrupts can be either falling edge, or either edge. Other external interrupts are either falling edge or active low. Tested on a custom 8280 based board. Signed-off-by:
Mark Ware <mware@elphinstone.net> Acked-by:
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- 09 Dec, 2009 34 commits
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Dmitry Eremin-Solenikov authored
Signed-off-by:
Dmitry Eremin-Solenikov <dbaryshkov@gmail.com> Signed-off-by:
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Dmitry Eremin-Solenikov authored
Describe all LocalBus chipselects on MPC8349E-MITX board. Also add flash bindings. Signed-off-by:
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Dmitry Eremin-Solenikov authored
Add OF descriptions of EEPROM, two GPIO extenders and SPD hanging on I2C on this board. Signed-off-by:
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Dmitry Eremin-Solenikov authored
mpc8349 bears two GPIO controllers. Enable support for them. Signed-off-by:
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Sebastian Andrzej Siewior authored
Signed-off-by:
Sebastian Andrzej Siewior <sebastian@breakpoint.cc> Signed-off-by:
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Anton Vorontsov authored
It appears that we wrongly calculate dev_base for type1 config cycles. The thing is: we shouldn't subtract hose->first_busno because PCI core sets PCI primary, secondary and subordinate bus numbers, and PCIe controller actually takes the registers into account. So we should use just bus->number. Also, according to MPC8315 reference manual, primary bus number should always remain 0. We have PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS quirk in indirect_pci.c, but since 83xx is somewhat special, it doesn't use indirect_pci.c routines, so we have to implement the quirk specifically for 83xx PCIe controllers. Signed-off-by:
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Benjamin Herrenschmidt authored
e821ea70 introduced a bug by copying some 64-bit originated code as-is to be used by both 32 and 64-bit but this code contains a 64-bit ony "cmpdi" instruction. This changes it to cmpwi, which is fine since VRSAVE can only contains a 32-bit value anyway. Signed-off-by:
Benjamin Herrenschmidt <benh@kernel.crashing.org> CC: <stable@kernel.org>
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Benjamin Herrenschmidt authored
Conflicts: include/linux/kvm.h
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Joe Perches authored
On Fri, 2009-12-04 at 20:59 +1100, Benjamin Herrenschmidt wrote: > On Fri, 2009-12-04 at 10:34 +0100, Jean Delvare wrote: > > I've sent it to linuxppc-dev@ozlabs.org on October 14th. This is the > > address which is listed 22 times in MAINTAINERS. If it isn't correct, > > then please update MAINTAINERS. > No it's fine both shoul work. Your patches are there, just waiting for > me to pick them up, I was just firing a reminder to the rest of the CC > list :-) (and I do remember fwd'ing a couple of your patches to the > list, for some reason they didn't make it to patchwork back then, that > was a few month ago). > Anyways, I've been stretched thin with all sort of stuff lately, so bear > with me if I'm a bit slow at taking or testing stuff, I'm doing my best. Adding patterns to the PowerPC sections of MAINTAINERS is useful. Signed-off-by:
Joe Perches <joe@perches.com> Acked-by:
Josh Boyer <jwboyer@linux.vnet.ibm.com> Acked-by:
Grant Likely <grant.likely@secretlab.ca> Acked-by:
Olof Johansson <olof@lixom.net> Acked-by:
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Mark Nelson authored
At the moment when we EOI an interrupt we set the CPPR back to 0xFF regardless of its previous value. This could lead to problems if we take an interrupt with a priority of 5, but before EOIing it we get an IPI which has a priority of 4. The problem is that at the moment when we EOI the IPI we will set the CPPR to 0xFF, but it should really be set back to 5 (the previous priority). To keep track of the previous CPPR values we create the xics_cppr structure that has an array for CPPR values and an index pointing to the current priority. This can easily grow if new priorities get added in the future. This will also be useful because the partition adjunct option of upcoming machines will update the H_XIRR hcall to accept the CPPR as a parameter. Signed-off-by:
Mark Nelson <markn@au1.ibm.com> Signed-off-by:
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Nathan Fontenot authored
The recent patch to add cpu offline/online as part of the DLPAR process for pseries causes a build break if CONFIG_SMP is not defined. Original patch here; http://lists.ozlabs.org/pipermail/linuxppc-dev/2009-November/078299.html This corrects the build break by moving the online_node_cpus and offline_node_cpus under the #ifdef CONFIG_ARCH_CPU_PROBE_RELEASE portions of dlpar.c. This patch also slightly modifies the online_node_cpus and offline_node_cpus routines to prepend dlpar_ to the them and make them static. These two routine are only used in the dlpar add/remove of cpus and these changes should help clarify that. Signed-off-by:
Nathan Fontenot <nfont@austin.ibm.com> Signed-off-by:
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Roman Fietze authored
Writing a driver using SCLPC on the MPC5200B I detected, that the intspec arrays to map irqs to Linux virq cannot be const, because the mapping and xlate functions only take non const pointers. All those functions do not modify the intspec, so a const pointer could be used. Signed-off-by:
Roman Fietze <roman.fietze@telemotive.de> Signed-off-by:
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Joakim Tjernlund authored
Use symbolic constant for PRESENT and avoid branching. Signed-off-by:
Joakim Tjernlund <Joakim.Tjernlund@transmode.se> Signed-off-by:
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Joakim Tjernlund authored
There is no need to do set the DIRTY bit directly in DTLB Error. Trap to do_page_fault() and let the generic MM code do the work. Signed-off-by:
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Joakim Tjernlund authored
Now that 8xx can fixup dcbX instructions, start using them where possible like every other PowerPc arch do. Signed-off-by:
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Joakim Tjernlund authored
8xx has not had WRITETHRU due to lack of bits in the pte. After the recent rewrite of the 8xx TLB code, there are two bits left. Use one of them to WRITETHRU. Perhaps use the last SW bit to PAGE_SPECIAL or PAGE_FILE? Signed-off-by:
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Joakim Tjernlund authored
only DTLB Miss did set this bit, DTLB Error needs too otherwise the setting is lost when the page becomes dirty. Signed-off-by:
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Joakim Tjernlund authored
This is an assembler version to fixup DAR not being set by dcbX, icbi instructions. There are two versions, one uses selfmodifing code, the other uses a jump table but is much bigger(default). Signed-off-by:
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Joakim Tjernlund authored
dcbz, dcbf, dcbi, dcbst and icbi do not set DAR when they cause a DTLB Error. Dectect this by tagging DAR with 0x00f0 at every exception exit that modifies DAR. Test for DAR=0x00f0 in DataTLBError and bail to handle_page_fault(). Signed-off-by:
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Joakim Tjernlund authored
Update the TLB asm to make proper use of _PAGE_DIRY and _PAGE_ACCESSED. Get rid of _PAGE_HWWRITE too. Pros: - I/D TLB Miss never needs to write to the linux pte. - _PAGE_ACCESSED is only set on TLB Error fixing accounting - _PAGE_DIRTY is mapped to 0x100, the changed bit, and is set directly when a page has been made dirty. - Proper RO/RW mapping of user space. - Free up 2 SW TLB bits in the linux pte(add back _PAGE_WRITETHRU ?) - kernel RO/user NA support. Cons: - A few more instructions in the TLB Miss routines. Signed-off-by: -
Joakim Tjernlund authored
8xx sometimes need to load a invalid/non-present TLBs in it DTLB asm handler. These must be invalidated separaly as linux mm don't. Signed-off-by:
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Benjamin Herrenschmidt authored
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Benjamin Herrenschmidt authored
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Gautham R Shenoy authored
Currently the cpu-allocation/deallocation process comprises of two steps: - Set the indicators and to update the device tree with DLPAR node information. - Online/offline the allocated/deallocated CPU. This is achieved by writing to the sysfs tunables "probe" during allocation and "release" during deallocation. At the sametime, the userspace can independently online/offline the CPUs of the system using the sysfs tunable "online". It is quite possible that when a userspace tool offlines a CPU for the purpose of deallocation and is in the process of updating the device tree, some other userspace tool could bring the CPU back online by writing to the "online" sysfs tunable thereby causing the deallocate process to fail. The solution to this is to serialize writes to the "probe/release" sysfs tunable with the writes to the "online" sysfs tunable. This patch employs a mutex to provide this serialization, which is a no-op on all architectures except PPC_PSERIES Signed-off-by:
Gautham R Shenoy <ego@in.ibm.com> Acked-by:
Vaidyanathan Srinivasan <svaidy@linux.vnet.ibm.com> Signed-off-by:
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Gautham R Shenoy authored
Currently the cpu-allocation/deallocation on pSeries is a two step process from the Userspace. - Set the indicators and update the device tree by writing to the sysfs tunable "probe" during allocation and "release" during deallocation. - Online / Offline the CPUs of the allocated/would_be_deallocated node by writing to the sysfs tunable "online". This patch adds kernel code to online/offline the CPUs soon_after/just_before they have been allocated/would_be_deallocated. This way, the userspace tool that performs DLPAR operations would only have to deal with one set of sysfs tunables namely "probe" and release". Signed-off-by:
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Valentine Barshak authored
Remove the CPU from the online map to prevent smp_call_function from sending messages to a stopped CPU. Signed-off-by:
Valentine Barshak <vbarshak@ru.mvista.com> Signed-off-by:
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Nathan Fontenot authored
This patch adds the specific routines to probe and release (add and remove) cpu resource for the powerpc pseries platform and registers these handlers with the ppc_md callout structure. Signed-off-by:
Paul Mackerras <paulus@samba.org> Signed-off-by:
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Nathan Fontenot authored
Version 3 of this patch is updated with documentation added to Documentation/ABI. There are no changes to any of the C code from v2 of the patch. In order to support kernel DLPAR of CPU resources we need to provide an interface to add (probe) and remove (release) the resource from the system. This patch Creates new generic probe and release sysfs files to facilitate cpu probe/release. The probe/release interface provides for allowing each arch to supply their own routines for implementing the backend of adding and removing cpus to/from the system. This also creates the powerpc specific stubs to handle the arch callouts from writes to the sysfs files. The creation and use of these files is regulated by the CONFIG_ARCH_CPU_PROBE_RELEASE option so that only architectures that need the capability will have the files created. Signed-off-by:
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Nathan Fontenot authored
The Dynamic Logical Partitioning capabilities of the powerpc pseries platform allows for the addition and removal of resources (i.e. CPU's, memory, and PCI devices) from a partition. The removal of a resource involves removing the resource's node from the device tree and then returning the resource to firmware via the rtas set-indicator call. To add a resource, it is first obtained from firmware via the rtas set-indicator call and then a new device tree node is created using the ibm,configure-coinnector rtas call and added to the device tree. This patch provides the kernel DLPAR infrastructure in a new filed named dlpar.c. The functionality provided is for acquiring and releasing a resource from firmware and the parsing of information returned from the ibm,configure-connector rtas call. Additionally this exports the pSeries reconfiguration notifier chain so that it can be invoked when device tree updates are made. Signed-off-by:
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Darrick J. Wong authored
In commit 0512a9a8, we unilaterally zero the "pwm invert" bit in the fan behavior configuration register. On my PowerBook G4, this results in the fans going to full speed at low temperature and shutting off at high temperature because the pwm invert bit is supposed to be set. Therefore, record the pwm invert bit at driver load time, and write the bit into the fan behavior control register. This restores correct behavior on my PBG4 and should work around the bit being set to the wrong value after suspend/resume (which is what the original patch was trying to fix). It also fixes a minor omission where the pwm invert bit correction is NOT performed when switching into automatic mode. Signed-off-by:
Darrick J. Wong <djwong@us.ibm.com> CC: <stable@kernel.org> Signed-off-by:
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Michel Dänzer authored
Signed-off-by:
Michel Dänzer <daenzer@vmware.com> Signed-off-by:
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Michel Dänzer authored
Also short-circuit empty updates. Signed-off-by:
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Dave Airlie authored
This allows offb to be used for initial framebuffer, and a kms driver to take over later in the boot sequence. Signed-off-by:
Dave Airlie <airlied@redhat.com> Signed-off-by:
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Benjamin Herrenschmidt authored
This is a libata driver for the "macio" IDE controller used on most Apple PowerMac and PowerBooks. It's a libata equivalent of drivers/ide/ppc/pmac.c It supports all the features of its predecessor, including mediabay hotplug and suspend/resume. It should also support module load/unload. The timing calculations have been simplified to use pre-calculated tables compared to drivers/ide/pmac.c and it uses the new mediabay interface provided by a previous patch. Signed-off-by:
Tejun Heo <tj@kernel.org>
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