- 19 Feb, 2009 1 commit
-
-
Russell King authored
This roughly corresponds with OMAP commits: 7d06c48d, 3241b19e, 88b5d9b6, 18a55008, 9c909ac9, 5c6497bc, 8b1f0bd4, 2ac1da8c. For both OMAP2 and OMAP3, we note the reference and bypass clocks in the DPLL data structure. Whenever we modify the DPLL rate, we first ensure that both the reference and bypass clocks are enabled. Then, we decide whether to use the reference and DPLL, or the bypass clock if the desired rate is identical to the bypass rate, and program the DPLL appropriately. Finally, we update the clock's parent, and then disable the unused clocks. This keeps the parents correctly balanced, and more importantly ensures that the bypass clock is running whenever we reprogram the DPLL. This is especially important because the procedure for reprogramming the DPLL involves switching to the bypass clock. Signed-off-by:
Russell King <rmk+kernel@arm.linux.org.uk>
-
- 14 Feb, 2009 1 commit
-
-
Russell King authored
linux-omap source commit 33d000c9 introduces a way to "dry run" clock changes before they're committed. However, this involves putting logic to handle this into each and every recalc function, and unfortunately due to the caching, led to some bugs. Solve both of issues by making the recalc methods always return the clock rate for the clock, which the caller decides what to do with. Signed-off-by:
-
- 08 Feb, 2009 38 commits
-
-
Paul Walmsley authored
Clock rate change code executes inside a spinlock with hardirqs disabled. The only code that should be messing around with the hardirq state should be the plat-omap/clock.c code. In the omap2_reprogram_dpllcore() case, this probably just wastes cycles, but in the omap3_core_dpll_m2_set_rate() case, this is a nasty bug. linux-omap source commit is b9b6208d. Signed-off-by:
Paul Walmsley <paul@pwsan.com> Signed-off-by:
Tony Lindgren <tony@atomide.com> Signed-off-by:
-
Russell King authored
Based on a patch from Paul Walmsley <paul@pwsan.com>: omap2_clk_enable() should enable a clock's clockdomain before attempting to enable its parent clock's clockdomain. Similarly, in the unlikely event that the parent clock enable fails, the clockdomain should be disabled. linux-omap source commit is 6d6e285e. Signed-off-by:
-
Russell King authored
Based upon a patch from Paul Walmsley <paul@pwsan.com>: If _omap2_clk_enable() fails, the clock's usecount must be decremented by one no matter whether the clock has a parent or not. but reorganised a bit. Signed-off-by: -
Paul Walmsley authored
This function is race-prone and mistakenly conveys the impression to drivers that it is part of the clock interface. Get rid of it: core code that absolutely needs this can just check clk->usecount. Drivers should not use it at all. linux-omap source commit is 5df9e4ad. Signed-off-by:
-
Paul Walmsley authored
Several parts of the OMAP2/3 clock code use wmb() to try to ensure that the hardware write completes before continuing. This approach is problematic: wmb() only ensures that the write leaves the ARM. It does not ensure that the write actually reaches the endpoint device. The endpoint device in this case - either the PRM, CM, or SCM - is three interconnects away from the ARM - and the final interconnect is low-speed. And the OCP interconnects will post the write, and who knows how long that will take to complete. So the wmb() is not what we want. Worse, the wmb() is indiscriminate; it causes the ARM to flush any other unrelated buffered writes and wait for the local interconnect to acknowledge them - potentially very expensive. Fix this by converting the wmb()s into readbacks of the same PRM/CM/SCM register. Since the PRM/CM/SCM devices use a single OCP thread, this will cause the MPU to block while waiting for posted writes to that device to complete. linux-omap source commit is 260f5487. Signed-off-by:
-
Paul Walmsley authored
Consolidate the commit code for DELAYED_APP clocks into a subroutine, _omap2xxx_clk_commit(). Also convert the MPU barrier wmb() into an OCP barrier, since with an MPU barrier, we have no guarantee that the write actually reached the endpoint device. linux-omap source commit is 0f5bdb73. Signed-off-by:
-
Paul Walmsley authored
clk_disable() previously used an ARM barrier, wmb(), to try to ensure that the hardware write completed before continuing. There are some problems with this approach. The first problem is that wmb() only ensures that the write leaves the ARM -- not that it actually reaches the endpoint device. In this case, the endpoint device - either the PRM, CM, or SCM - is three interconnects away from the ARM, and the final interconnect is low-speed. And the OCP interconnects will post the write, who knows how long that will take to complete. So the wmb() is not really what we want. Worse, the wmb() is indiscriminate; it will cause the ARM to flush any other unrelated buffered writes and wait for the local interconnect to acknowledge them - potentially very expensive. This first problem could be fixed by doing a readback of the same PRM/CM/SCM register. Since these devices use a single OCP thread, this will cause the MPU to wait for the write to complete. But the primary problem is a conceptual one: clk_disable() should not need any kind of barrier. clk_enable() needs one since device driver code must not access a device until its clocks are known to be enabled. But clk_disable() has no such restriction. Since blocking the MPU on a PRM/CM/SCM write can be a very high-latency operation - several hundred MPU cycles - it's worth avoiding this barrier if possible. linux-omap source commit is f4aacad2. Signed-off-by:
-
Russell King authored
Traditionally, we've tracked the parent/child relationships between clk structures by setting the child's parent member to point at the upstream clock. As a result, when decending the tree, we have had to scan all clocks to find the children. Avoid this wasteful scanning by keeping a list of the clock's children. Signed-off-by: -
Russell King authored
This implements the remainder of: OMAP clock: move rate recalc, propagation code up to plat-omap/clock.c from Paul Walmsley which is not covered by the previous: [ARM] omap: move clock propagation into core omap clock code [ARM] omap: remove unnecessary calls to propagate_rate() [ARM] omap: move propagate_rate() calls into generic omap clock code commits. Signed-off-by: -
Paul Walmsley authored
Use the standard clk_set_rate() function in omap2_clk_arch_init() rather than omap2_select_table_rate() -- this will ensure that clock rates are recalculated and propagated correctly after those operations are consolidated into clk_set_rate(). linux-omap source commit is 03c03330. Signed-off-by:
-
Tero Kristo authored
Current implementation will disable clocks in the order defined in clock34xx.h, at least DPLL4_M2X2 will hang in certain cases (and prevent retention / off) if clocks are not disabled in correct order. This patch makes sure the parent clocks will be active when disabling a clock. linux-omap source commit is 67268006. Signed-off-by:
Tero Kristo <tero.kristo@nokia.com> Signed-off-by:
Kevin Hilman <khilman@deeprootsystems.com> Signed-off-by:
-
Paul Walmsley authored
Add the omap3_core_dpll_m2_set_rate() function to the OMAP3 clock code, which calls into the SRAM function omap3_sram_configure_core_dpll() to change the CORE DPLL M2 divider. (SRAM code is necessary since rate changes on clocks upstream from the SDRC can glitch SDRAM accesses.) Use this function for the set_rate function pointer in the dpll3_m2_ck struct clk. With this function in place, PM/OPP code should be able to alter SDRAM speed via code similar to: clk_set_rate(&dpll3_m2_ck, target_rate). linux-omap source commit is 7f8b2b0f. Signed-off-by: -
Paul Walmsley authored
For a given SDRAM clock rate, SDRAM chips require memory controllers to use a specific set of timing minimums and maximums to transfer data reliably. These parameters can be different for different memory chips and can also potentially vary by board. This patch adds the infrastructure for board-*.c files to pass this timing data to the SDRAM controller init function. The timing data is specified in an 'omap_sdrc_params' structure, in terms of SDRC controller register values. An array of these structs, one per SDRC target clock rate, is passed by the board-*.c file to omap2_init_common_hw(). This patch does not define the values for different memory chips, nor does it use the values for anything; those will come in subsequent patches. linux-omap source commit is bc84ecfc. Signed-off-by:
-
Paul Walmsley authored
Separate SDRC code common to OMAP2/3 from mach-omap2/sdrc2xxx.c to mach-omap2/sdrc.c. Rename the OMAP2xxx-specific functions to use an 'omap2xxx' prefix rather than an 'omap2' prefix, and use "sdrc" in the function names rather than "memory." Mark several functions as static that should not be used outside the sdrc2xxx.c file. linux-omap source commit is bf1612b9. Signed-off-by:
-
Paul Walmsley authored
Rename arch/arm/mach-omap2/memory.c to arch/arm/mach-omap2/sdrc2xxx.c, since it contains exclusively SDRAM-related functions. Most of the functions are also OMAP2xxx-specific - those which are common will be separated out in a following patch. linux-omap source commit is fe212f79. Signed-off-by:
-
Paul Walmsley authored
Move the contents of the arch/arm/mach-omap2/memory.h file to the existing mach/sdrc.h file, and remove memory.h. Modify files which include memory.h to include asm/arch/sdrc.h instead. linux-omap source commit is e7ae2d89. Signed-off-by:
-
Tony Lindgren authored
This fixes booting, and is a step toward fixing things properly: - Make enable_reg u32 instead of u16 [rmk: virtual addresses are void __iomem *, not u32] - Get rid of VIRTUAL_IO_ADDRESS for clocks - Use __raw_read/write instead of omap_read/write for clock registers This patch adds a bunch of compile warnings until omap1 clock also uses offsets. linux-omap source commit is 9d1dff86. Signed-off-by:
-
Paul Walmsley authored
This patch fixes a few OMAP2xxx CM_IDLEST bits that were incorrectly marked as being OMAP2xxx-wide, when they were actually 2420-specific. Also, originally when the PRCM register macros were defined, bit shift macros used a "_SHIFT" suffix, and mask macros used none. This became a source of bugs and confusion, as the mask macros were mistakenly used for shift values. Gradually, the mask macros have been updated, piece by piece, to add a "_MASK" suffix on the end to clarify. This patch applies this change to the CM_IDLEST_* register bits. The patch also adds a few bits that were missing, mostly from the 3430ES1 to ES2 revisions. linux-omap source commits are d18eff5b, e1f1a5cc, and part of 9fe6b6cfSigned-off-by:
-
Jouni Hogander authored
Signed-off-by:
Jouni Hogander <jouni.hogander@nokia.com> Signed-off-by:
-
Paul Walmsley authored
This patch rolls up several cleanup patches. 1. Some unnecessarily verbose variable names are used in several clock.c functions; clean these up per CodingStyle. 2. Remove omap2_get_clksel() and just use clk->clksel_reg and clk->clksel_mask directly. 3. Get rid of void __iomem * usage in omap2_clksel_get_src_field. Prepend the function name with an underscore to highlight that it is a static function. linux-omap source commits are 7fa95e00, af0ea23f, and 91c0c979. Signed-off-by:
-
Paul Walmsley authored
During _omap3_noncore_dpll_lock(), if a DPLL has no active downstream clocks and DPLL autoidle is enabled, the DPLL may never lock, since it will enter autoidle immediately. To resolve this, disable DPLL autoidle while locking the DPLL, and unconditionally wait for the DPLL to lock. This fixes some bugs where the kernel would hang when returning from retention or return the wrong rate for the DPLL. This patch is a collaboration with Peter de Schrijver <peter.de-schrijver@nokia.com> and Kevin Hilman <khilman@deeprootsystems.com>. linux-omap source commit is 3b7de4be. Signed-off-by:
-
Paul Walmsley authored
The DPLL FREQSEL jitter correction bits are set based on a table in the 34xx TRM, Table 4-38, according to the DPLL's internal clock frequency "Fint." Several Fint frequency ranges are missing from this table. Previously, we allowed these Fint frequency ranges to be selected in the rate rounding code, but did not change the FREQSEL bits. Correspondence with the OMAP hardware team indicates that Fint values not in the table should not be used. So, prevent them from being selected during DPLL rate rounding. This removes warnings and also can prevent the chip from locking up. The first pass through the rate rounding code will update the DPLL max and min dividers appropriately, so later rate rounding passes will run faster than the first. Peter de Schrijver <peter.de-schrijver@nokia.com> put up with several test cycles of this patch - thanks Peter. linux-omap source commit is f9c1b82f. Signed-off-by:
-
Paul Walmsley authored
The previous DPLL rate rounding algorithm counted the divider (N) down from the maximum to 1. Since we currently use a broad DPLL rate tolerance, and lower N values are more power-efficient, we can often bypass several iterations through the loop by counting N upwards from 1. Peter de Schrijver <peter.de-schrijver@nokia.com> put up with several test cycles of this patch - thanks Peter. linux-omap source commit is 6f6d82bb. Signed-off-by:
-
Paul Walmsley authored
Remove some clutter from omap2_dpll_round_rate(). linux-omap source commit is 4625dceb. Signed-off-by:
-
Paul Walmsley authored
Convert struct dpll_data.idlest_bit field to idlest_mask. Needed since OMAP2 uses two bits for DPLL IDLEST rather than one. While here, add the missing idlest_* fields for DPLL3. linux-omap source commits are 25bab0f1 and b0f7fd17. Signed-off-by:
-
Paul Walmsley authored
OMAP34xx ES2 TRM Delta G to H states that the divider for DPLL1_FCLK and DPLL2_FCLK can divide by 4 in addition to dividing by 1 and 2. Encode this into the OMAP3 clock framework. linux-omap source commit is 050684c1. Signed-off-by:
-
Paul Walmsley authored
Fix DPLL jitter correction programming. Previously, omap3_noncore_dpll_program() stored the FREQSEL jitter correction parameter to the wrong register. This caused jitter correction to be set incorrectly and also caused the DPLL divider to be programmed incorrectly. Also, fix DPLL divider programming. An off-by-one error existed in omap3_noncore_dpll_program(), causing DPLLs to be programmed with a higher divider than intended. linux-omap source commit is 5c0ec88a. Signed-off-by:
-
Jouni Hogander authored
Using sdti doesn't keep emu_pwrdm on if hardware supervised pwrdm transitions are used. This causes sdti stop to work when power management is initialized and hardware supervised pwrdm control is enabled. This patch disables hardware supervised pwrdm control for emu_pwrdm. Now emu_pwrdm is switched off on boot by software when it is not used. Signed-off-by:
-
Paul Walmsley authored
Fix the clockdomain autodep code to respect omap_chip platform flags. Resolves "Unable to handle kernel paging request at virtual address 5f75706d" panic during power management initialization on OMAP2. Signed-off-by:
-
Tomi Valkeinen authored
Enabling clock in a disabled power domain causes the power domain to be turned on. However, the power transition is not always finished when clk_enable() returns and this randomly crashes the kernel when an interrupt happens right after the clk_enable, and the kernel tries to read the irq status register for that domain. Why the irq status register is inaccessible, I don't know. Also it doesn't seem to be related to the module being not powered up, but to the transition itself. The same could perhaps happen after clk_disable also, but I have not witnessed that. The problem affects at least dss, cam and sgx clocks. This change waits for the transition to be finished before returning from omap2_clkdm_clk_enable(). Signed-off-by:
Tomi Valkeinen <tomi.valkeinen@nokia.com> Signed-off-by:
-
Paul Walmsley authored
The SGX device on OMAP3 does not support retention, so remove RET from the list of possible SGX power states. Problem debugged by Richard Woodruff <r-woodruff2@ti.com>. Signed-off-by:
Richard Woodruff <r-woodruff2@ti.com> Signed-off-by:
-
Paul Walmsley authored
Each DPLL exists in its own powerdomain (cf 34xx TRM figure 4-18) and clockdomain; so, create powerdomain and clockdomain structures for them. Mark each DPLL clock as belonging to their respective DPLL clockdomain. cf. 34xx TRM Table 4-27 (among other references). linux-omap source commits are acdb6158 and a8798a48. Signed-off-by:
-
Paul Walmsley authored
sys_clkout2 belongs in the core_clkdm (3430 TRM section 4.7.2.2). It's not clear whether it actually is in the CORE clockdomain, or whether it is technically in a different clockdomain; but this is closer to reality than the present configuration. Signed-off-by:
-
Paul Walmsley authored
Add clockdomains for the CM and PRM. These will ultimately replace the "wkup_clkdm", which appears to not actually exist on the hardware. Signed-off-by:
-
Paul Walmsley authored
struct clockdomain contains a struct powerdomain *pwrdm and const char *pwrdm_name. The pwrdm_name is only used at initialization to look up the appropriate pwrdm pointer. Combining these into a union saves about 100 bytes on 3430SDP. This patch should not cause any change in kernel function. Updated to gracefully handle autodeps that contain invalid powerdomains, per Russell King's review comments. Boot-tested on BeagleBoard ES2.1. linux-omap source commit is 718fc6cd. Signed-off-by:
-
Kevin Hilman authored
This patch adds a CPUfreq frequency-table implementation for OMAP2 by walking the PRCM rate-table for available entries and adding them to a CPUfreq table. CPUfreq can then be used to manage switching between all the available entries in the PRCM rate table. Either use the CPUfreq sysfs interface directly, (see Section 3 of Documentation/cpu-freq/user-guide.txt) or use the cpufrequtils package: http://www.kernel.org/pub/linux/utils/kernel/cpufreq/cpufrequtils.htmlSigned-off-by:
Kevin Hilman <khilman@mvista.com> Updated to try to use cpufreq_table if it exists. linux-omap source commit is 77ce544f. Signed-off-by:
-
Paul Walmsley authored
Filling the set_rate and round_rate fields of dpll4_m4_ck makes this clock programmable through clk_set_rate(). This is needed to give omapfb control over the dss1_alwon_fck rate. This patch includes a fix from Tomi Valkeinen <tomi.valkeinen@nokia.com>. linux-omap source commits are e42218d4 and 9d211b76. Signed-off-by:
Måns Rullgård <mans@mansr.com> Signed-off-by:
-
Sergio Aguirre authored
Add CSI2 clock struct for handling it with clock API when TI PM is disabled. linux-omap source commit is 8b20f449. Signed-off-by:
Sergio Aguirre <saaguirre@ti.com> Acked-by:
-
