- 28 Oct, 2005 40 commits
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Nicolas Pitre authored
Patch from Nicolas Pitre From: Daniel Jacobowitz <dan@debian.org> > I also fixed a bug that confused me greatly while trying to debug: one > SIGILL has long been a SIGSEGV because of some broken RISCOS > compatibility code. Signed-off-by:
Nicolas Pitre <nico@cam.org> Signed-off-by:
Russell King <rmk+kernel@arm.linux.org.uk>
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Jon Ringle authored
Patch from Jon Ringle This adds support for the RTC and nvram on the Comdial MP1000 Signed-off-by: Jon Ringle Signed-off-by: -
Matt Reimer authored
Patch from Matt Reimer Adds support for HWUART on PXA 255 / 26x. This patch originally came from http://svn.rungie.com/svn/gumstix-buildroot/trunk/sources/kernel-patches/000-gumstix-hwuart.patch and has been tweaked by me. Signed-off-by:
Matt Reimer <mreimer@vpop.net> Signed-off-by:
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Todd Poynor authored
Patch from Todd Poynor Add symbols for PXA2xx PWRMODE register M field that selects low-power mode, replace unadorned constants. Honor power mode parameter of pxa_cpu_suspend(mode), no longer force to 3 (sleep). Full Deep Sleep low-power mode support for PXA27x is pending generic PM interfaces to select more than 2 suspend-to-RAM-style power modes, but this is expected soon. This can be hardcoded in the meantime by replacing the pxa_cpu_suspend() parameter value. From David Burrage and Todd Poynor. Try #2 removes one of the register copies and moves the code to save the pxa_cpu_suspend parameter to immediately surround the call that requires the parameter value be preserved. Signed-off-by:
Todd Poynor <tpoynor@mvista.com> Signed-off-by:
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Jon Ringle authored
Patch from Jon Ringle This patch gives support for the CS8900A ethernet chip on the Comdial MP1000 Signed-off-by: Jon Ringle Signed-off-by: -
Jon Ringle authored
Patch from Jon Ringle Updated 2898/1 per comments: - Removed fixup - Moved code in mach-mp1000/ to mach-clps711x/ - Cleaned up code in mp1000-seprom.c. Eliminated code that displayed the contents of the eeprom Please comment. Signed-off-by: Jon Ringle Signed-off-by: -
Ian Campbell authored
Patch from Ian Campbell As noted by Uli Luckas in the comments of 3025 there is a typo in the i2s platform device. The i2s platform device refers to the i2c resources. Signed-off-by:
Ian Campbell <icampbell@arcom.com> Signed-off-by:
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Ben Dooks authored
Patch from Ben Dooks Add platform data for framebuffer for the onboard LCD module Signed-off-by:
Ben Dooks <ben-linux@fluff.org> Signed-off-by:
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Ben Dooks authored
Patch from Ben Dooks Add framebuffer platform data Signed-off-by:
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Ben Dooks authored
Patch from Ben Dooks Change set_s3c2410fb_info to s3c2410_fb_set_platdata and use kmalloc() for the copy of the information it is passed. Signed-off-by:
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Lennert Buytenhek authored
Patch from Lennert Buytenhek We already had a mapping for the msf, but we didn't have any register definitions for it yet. Signed-off-by:
Lennert Buytenhek <buytenh@wantstofly.org> Signed-off-by:
Deepak Saxena <dsaxena@plexity.net> Signed-off-by:
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Ian Campbell authored
[ARM] 3044/1: Fix sparse warnings about incompatible pointer types for register defined in pxa-regs.h Patch from Ian Campbell The sparse warning initially surfaced in sound/arm/pxa2xx-ac97.c because it was using u32 * variables to hold the unsigned long * register addresses. I submitted an ALSA patch for this http://thread.gmane.org/gmane.linux.alsa.devel/27804 issue and it was suggested that it might be preferable to change the register definitions to use u32. Most other subarches seem to use u32 for their register type, at least the ones which use a __REG macro (like the PXA) do. Nico indicated in the thread above that he wouldn't mind this patch. Changing the type required fixes for opposite warnings in the pxa2xx usb gadget code but that was the only new warning introduced on defconfig or lubbock, mainstone and our own PXA255 boards. Signed-off-by:
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Ben Dooks authored
Patch from Ben Dooks From: Guillaume GOURAT <guillaume.gourat@nexvision.fr> A number of devices have an extra byte on the end of their areas due to mis-calculating the .end field of their resources Signed-off-by:
Guillaume GOURAT <guillaume.gourat@nexvision.fr> Signed-off-by:
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Ben Dooks authored
Patch from Ben Dooks Add generic values for the parameters to the s3c2410_gpio_cfgpin() function, so that a caller does not need to know the exact constant for the specified pin. This is very useful for the case where a driver is passed a gpio pin number and needs to reconfigure the pin's function. Signed-off-by:
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Nicolas Pitre authored
Patch from Nicolas Pitre Here's an ARM assembly SHA1 implementation to replace the default C version. It is approximately 50% faster than the generic C version. On an XScale processor running at 400MHz: generic C version: 9.8 MB/s my version: 14.5 MB/s This code is useful to quite a few callers in the tree: crypto/sha1.c: sha_transform(sctx->state, sctx->buffer, temp); crypto/sha1.c: sha_transform(sctx->state, &data[i], temp); drivers/char/random.c: sha_transform(buf, (__u8 *)r->pool+i, buf + 5); drivers/char/random.c: sha_transform(buf, (__u8 *)data, buf + 5); net/ipv4/syncookies.c: sha_transform(tmp + 16, (__u8 *)tmp, tmp + 16 + 5); Signed-off-by:
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Deepak Saxena authored
Patch from Deepak Saxena This patch adds support for 36-bit static mapped I/O. While there are no platforms in the tree ATM that use it, it has been tested tested on the IXP2350 NPU and I would like to get the support for that chipset upstream one piece at a time. There are also other Intel chipset ports in development that are waiting on this to go upstream. The patch replaces the print formats for physical addresses with %016llx which will create a bit extraneous output on 32-bit systems, but I think that is cleaner than having #ifdefs, specially since users will only see the output in error cases. Depends on 3016/1. Signed-off-by:
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Deepak Saxena authored
Patch from Deepak Saxena Convert map_desc.physical to map_desc.pfn. This allows us to add support for 36-bit addressed physical devices in the static maps without having to resort to u64 variables. Signed-off-by:
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Deepak Saxena authored
Patch from Deepak Saxena Integrator map_desc.pfn conversion Signed-off-by:
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Deepak Saxena authored
Patch from Deepak Saxena iMX map_desc.pfn conversion Signed-off-by:
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Deepak Saxena authored
Patch from Deepak Saxena H720x map_desc.pfn conversion Signed-off-by:
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Deepak Saxena authored
Patch from Deepak Saxena Footbridge map_desc.pfn conversion Signed-off-by:
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Deepak Saxena authored
Patch from Deepak Saxena EBSA110 map_desc.pfn conversion Signed-off-by:
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Deepak Saxena authored
Patch from Deepak Saxena EPXA10DB mapd_desc.pfn conversion Signed-off-by:
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Deepak Saxena authored
Patch from Deepak Saxena Versatile map_desc.pfn conversion Signed-off-by:
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Deepak Saxena authored
Patch from Deepak Saxena CLSP7500 map_desc.pfn conversion Signed-off-by:
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Deepak Saxena authored
Patch from Deepak Saxena CLSP711x map_desc.pfn conversion Signed-off-by:
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Deepak Saxena authored
Patch from Deepak Saxena SA1100 map_desc.pfn conversion Signed-off-by:
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Deepak Saxena authored
Patch from Deepak Saxena Shark map_desc.pfn conversion Signed-off-by:
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Deepak Saxena authored
Patch from Deepak Saxena S3C2410 map_desc.pfn conversion Signed-off-by:
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Deepak Saxena authored
Patch from Deepak Saxena RiscPC map_desc.pfn conversion Signed-off-by:
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Deepak Saxena authored
Patch from Deepak Saxena PXA map_desc.pfn conversion Signed-off-by:
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Deepak Saxena authored
Patch from Deepak Saxena OMAP map_desc.pfn conversion Signed-off-by:
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Deepak Saxena authored
Patch from Deepak Saxena LH7A40x map_desc.pfn conversion Signed-off-by:
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Deepak Saxena authored
Patch from Deepak Saxena IXP4xx map_desc.pfn conversion Signed-off-by:
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Deepak Saxena authored
Patch from Deepak Saxena IXP2000 map_desc.pfn conversion Signed-off-by:
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Deepak Saxena authored
Patch from Deepak Saxena IOP3xx map_desc.pfn conversion Signed-off-by:
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Deepak Saxena authored
Patch from Deepak Saxena aaec2000 map_desc.pfn conversion Signed-off-by:
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Russell King authored
There is nothing special about having the init code separate from the common code, so combine the two. Signed-off-by: -
Russell King authored
The common oprofile code assumes the name "PMU" (from Intel's performance management unit). This is misleading when we start adding oprofile support for other machine types which don't use the same terminology. Call it op_arm_* instead of pmu_*. Signed-off-by: -
Russell King authored
The oprofile suspend/resume was missing locking. If we failed to start oprofile on resume, we still reported that it was enabled. Instead, disable oprofile on error. Signed-off-by:
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