- 11 Sep, 2009 3 commits
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Paul Mackerras authored
Currently there is a bug where if you use oprofile on a pSeries machine, then use perf_counters, then use oprofile again, oprofile will not work correctly; it will lose the PMU configuration the next time the hypervisor does a partition context switch, and thereafter won't count anything. Maynard Johnson identified the sequence causing the problem: - oprofile setup calls ppc_enable_pmcs(), which calls pseries_lpar_enable_pmcs, which tells the hypervisor that we want to use the PMU, and sets the "PMU in use" flag in the lppaca. This flag tells the hypervisor whether it needs to save and restore the PMU config. - The perf_counter code sets and clears the "PMU in use" flag directly as it context-switches the PMU between tasks, and leaves it clear when it finishes. - oprofile setup, called for a new oprofile run, calls ppc_enable_pmcs, which does nothing because it has already been called. In particular it doesn't set the "PMU in use" flag. This fixes the problem by arranging for ppc_enable_pmcs to always set the "PMU in use" flag. It makes the perf_counter code call ppc_enable_pmcs also rather than calling the lower-level function directly, and removes the setting of the "PMU in use" flag from pseries_lpar_enable_pmcs, since that is now done in its caller. This also removes the declaration of pasemi_enable_pmcs because it isn't defined anywhere. Reported-by:
Maynard Johnson <mpjohn@us.ibm.com> Signed-off-by:
Paul Mackerras <paulus@samba.org> Cc: <stable@kernel.org) Signed-off-by:
Benjamin Herrenschmidt <benh@kernel.crashing.org>
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Kumar Gala authored
The following commit introduced a compile error since it removed the implementation of smp_85xx_basic_setup: commit 77c0a700 Author: Benjamin Herrenschmidt <benh@kernel.crashing.org> Date: Fri Aug 28 14:25:04 2009 +1000 powerpc: Properly start decrementer on BookE secondary CPUs Make it so that smp_ops probe() and setup_cpu() can be set to NULL. Signed-off-by:
Kumar Gala <galak@kernel.crashing.org> Signed-off-by:
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Wolfram Sang authored
The OF helpers look like nanodoc but are missing the header. Fix this and a typo (s/nad/and/) while we are here. Signed-off-by:
Wolfram Sang <w.sang@pengutronix.de> Signed-off-by:
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- 02 Sep, 2009 6 commits
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Benjamin Herrenschmidt authored
A misconfiguration by the firmware of the U4 PCIe bridge on PowerMac G5 with the U4 bridge (latest generations, may also affect the iMac G5 "iSight") is causing us to re-assign the PCI BARs of the video card, which can get it out of sync with the firmware, thus breaking offb. This works around it by fixing up the bridge configuration properly at boot time. It also fixes a bug where the firmware provides us with an incorrect set of accessible regions in the device-tree. Signed-off-by: -
Kumar Gala authored
Switch to using the Power ISA defined PTE format when we have a 64-bit PTE. This makes the code handling between fsl-booke and book3e-64 similiar for TLB faults. Additionally this lets use take advantage of the page size encodings and full permissions that the HW PTE defines. Also defined _PMD_PRESENT, _PMD_PRESENT_MASK, and _PMD_BAD since the 32-bit ppc arch code expects them. Signed-off-by:
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Kumar Gala authored
Add defines for the other page sizes. Even if HW doesn't support them we made them use them for hugetlbfs support. Signed-off-by:
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Brian King authored
The SLB can change sizes across a live migration, which was not being handled, resulting in possible machine crashes during migration if migrating to a machine which has a smaller max SLB size than the source machine. Fix this by first reducing the SLB size to the minimum possible value, which is 32, prior to migration. Then during the device tree update which occurs after migration, we make the call to ensure the SLB gets updated. Also add the slb_size to the lparcfg output so that the migration tools can check to make sure the kernel has this capability before allowing migration in scenarios where the SLB size will change. BenH: Fixed #include <asm/mmu-hash64.h> -> <asm/mmu.h> to avoid breaking ppc32 build Signed-off-by:Brian King <brking@linux.vnet.ibm.com> Signed-off-by:
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Lyonel Vincent authored
On certain PowerMacs, a module (therm_windtunnel) controls various thermal settings (it can report CPU/case temperature, change speed of internal fans, etc.) By default, the hardware thermal control has a temperature limit to protect the computer from damages (the default limit seems to be 80°C) but therm_windtunnel.c reduces it to an anormaly low value (65°C), which means that he computer will shut down randomly when hit by direct sun light or during summer (summer in France can be quite hot), actually possibly losing data instead of protecting it. The overheat limit in therm_windtunnel.c:253-254 should be set to 75°C and 70°C instead of 65°C and 60°C respectively. From: Lyonel Vincent <lyonel@ezix.org> Signed-off-by:
Bartlomiej Zolnierkiewicz <bzolnier@gmail.com> Signed-off-by:
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Grant Likely authored
The two versions are doing almost exactly the same thing. No need to maintain them as separate files. This patch also has the side effect of making the PCI device tree scanning code available to 32 bit powerpc machines, but no board ports actually make use of this feature at this point. Signed-off-by:
Grant Likely <grant.likely@secretlab.ca> Acked-by:
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- 31 Aug, 2009 6 commits
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Tiejun Chen authored
To support cuImage, we need to initialize the required sections and ensure that it is built. Signed-off-by:
Tiejun Chen <tiejun.chen@windriver.com> Signed-off-by:
Josh Boyer <jwboyer@linux.vnet.ibm.com>
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Tiejun Chen authored
For cuImage format it's necessary to provide clock fixups since u-boot will not pass necessary clock frequency into the dtb included into cuImage so we implement the clock fixups as defined in the technical documentation for the board and update header file with the basic register definitions. Signed-off-by:
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Solomon Peachy authored
This patch adds support for the ESTeem 195E Hotfoot SBC. There are several variants of the SBC deployed, single/dual ethernet+serial, and also 4MB/8MB flash variations. In the interest of having a single kernel image boot on all boards, the cuboot shim detects the differences and mangles the DTS tree appropriately. With the exception of the CF interface that was never populated on production boards, this code/DTS supports all boardpop options. Signed-off-by:
Solomon Peachy <solomon@linux-wlan.com> Signed-off-by:
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fkan@amcc.com authored
This patch adds support for the AMCC (AppliedMicro) PPC460SX Eiger evaluation board. Signed-off-by:
Tai Tri Nguyen <ttnguyen@amcc.com> Acked-by:
Feng Kan <fkan@amcc.com> Acked-by:
Tirumala Marri <tmarri@amcc.com> Signed-off-by:
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Stefan Roese authored
This patch adds NOR MTD support and I2C HWMON support for the AD7414 to the AMCC Arches defconfig. Signed-off-by:
Stefan Roese <sr@denx.de> Signed-off-by:
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Stefan Roese authored
This patch adds some nodes to the AMCC Arches dts: - L2 cache support - NOR FLASH mapping with default partitioning - I2C HWMON device (AD7414) Signed-off-by:
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- 28 Aug, 2009 21 commits
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Benjamin Herrenschmidt authored
This moves the code to start the decrementer on 40x and BookE into a separate function which is now called from time_init() and secondary_time_init(), before the respective clock sources are registered. We also remove the 85xx specific code for doing it from the platform code. Signed-off-by: -
Paul Gortmaker authored
The default COMMAND_LINE_SIZE in asm-generic is 512, so the net effect of this change is nil, aside from the cleanup factor. See also commit 2b74b856. Signed-off-by:
Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by:
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Kumar Gala authored
Some of the PCI features we have in ppc32 we will need on ppc64 platforms in the future. These include support for: * ppc_md.pci_exclude_device * indirect config cycles * early config cycles We also simplified the logic in fake_pci_bus() to assume it will always get a valid pci_controller. Since all current callers seem to pass it one. Signed-off-by:
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Grant Likely authored
The PCI device tree scanning code in pci_64.c is some useful functionality. It allows PCI devices to be described in the device tree instead of being probed for, which in turn allows pci devices to use all of the device tree facilities to describe complex PCI bus architectures like GPIO and IRQ routing (perhaps not a common situation for desktop or server systems, but useful for embedded systems with on-board PCI devices). This patch moves the device tree scanning into pci-common.c so it is available for 32-bit powerpc machines too. Signed-off-by:
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Grant Likely authored
PPC_OF is always selected for arch/powerpc. This patch removes the stale #defines Signed-off-by:
Stephen Rothwell <sfr@canb.auug.org.au> Acked-by:
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Kumar Gala authored
We now search through TLBnCFG looking for the first array that has IPROT support (we assume that there is only one). If that TLB has hardware entry select (HES) support we use the existing code and with the proper TLB select (the HES code still needs to clean up bolted entries from firmware). The non-HES code is pretty similiar to the 32-bit FSL Book-E code but does make some new assumtions (like that we have tlbilx) and simplifies things down a bit. Signed-off-by:
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Kumar Gala authored
Not all 64-bit Book-3E parts will have fixed IVORs so add a function that cpusetup code can call to setup the base IVORs (0..15) to match the fixed offsets. We need to 'or' part of interrupt_base_book3e into the IVORs since on parts that have them the IVPR doesn't extend as far down. Signed-off-by:
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Kumar Gala authored
Match what we do on 32-bit Book-E processors and enable the decrementer in generic_calibrate_decr. We need to make sure we disable the decrementer early in boot since we currently use lazy (soft) interrupt on 64-bit Book-E and possible get a decrementer exception before we are ready for it. Signed-off-by:
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Kumar Gala authored
Move the default cpu entry table for CONFIG_PPC_BOOK3E_64 to the very end since we will probably want to support both 32-bit and 64-bit kernels for some processors that are higher up in the list. Signed-off-by:
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Kumar Gala authored
Support for TLB reservation (or TLB Write Conditional) and Paired MAS registers are optional for a processor implementation so we handle them via MMU feature sections. We currently only used paired MAS registers to access the full RPN + perm bits that are kept in MAS7||MAS3. We assume that if an implementation has hardware page table at this time it also implements in TLB reservations. Signed-off-by:
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Michael Wolf authored
On POWER6 systems RA needs to be the base and RB the index. If they are reversed you take a misdirect hit. Signed-off-by:
Mike Wolf <mjwolf@us.ibm.com> ---- Signed-off-by:
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Becky Bruce authored
Previously, the 36-bit code was using these bits, but they had never been named in the pte format definition. This patch just gives those fields their proper names and adds a comment that they are only present on some processors. There is no functional code change. Signed-off-by:
Becky Bruce <beckyb@kernel.crashing.org> Signed-off-by:
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Peter Huewe authored
Trivial patch which adds the __init/__exit macros to the module_init/ module_exit functions of char/hvc_vio.c Please have a look at the small patch and either pull it through your tree, or please ack' it so Jiri can pull it through the trivial tree. linux version 2.6.31-rc6 - linus git tree, Do 20. Aug 22:26:06 CEST 2009 Signed-off-by:
Peter Huewe <peterhuewe@gmx.de> Signed-off-by:
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FUJITA Tomonori authored
Signed-off-by:
FUJITA Tomonori <fujita.tomonori@lab.ntt.co.jp> Signed-off-by:
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FUJITA Tomonori authored
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FUJITA Tomonori authored
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FUJITA Tomonori authored
This converts uses dma_map_ops struct (in include/linux/dma-mapping.h) instead of POWERPC homegrown dma_mapping_ops. Signed-off-by:
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FUJITA Tomonori authored
POWERPC needs this hook. SPARC could use it too. Signed-off-by:
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FUJITA Tomonori authored
Now swiotlb_pci_dma_ops is identical to swiotlb_dma_ops; we can use swiotlb_dma_ops with any devices. This removes swiotlb_pci_dma_ops. Signed-off-by:
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FUJITA Tomonori authored
This patch adds max_direct_dma_addr to struct dev_archdata to remove addr_needs_map in struct dma_mapping_ops. It also converts dma_capable() to use max_direct_dma_addr. max_direct_dma_addr is initialized in pci_dma_dev_setup_swiotlb(), called via ppc_md.pci_dma_dev_setup hook. For further information: http://marc.info/?t=124719060200001&r=1&w=2Signed-off-by:
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Benjamin Herrenschmidt authored
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- 27 Aug, 2009 4 commits
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Benjamin Herrenschmidt authored
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Gautham R Shenoy authored
Time time taken for a single cpu online operation on a pseries machine is as follows: Dedicated LPAR (POWER6): ~220ms. Shared LPAR (POWER5) : ~240ms. Of this time, approximately 200ms is taken up by __cpu_up(). This is because we poll every 200ms to check if the new cpu has notified it's presence through the cpu_callin_map. We repeat this operation until the new cpu sets the value in cpu_callin_map or 5 seconds elapse, whichever comes earlier. However, using completion_structs instead of polling loops, the time taken by the new processor to indicate it's presence has found to be less than 1ms on pseries. This method however may not work on all powerpc platforms due to the time-base synchronization code. Keeping this in mind, we could reduce msleep polling interval from 200ms to 1ms while retaining the 5 second timeout. With this, the time taken for a cpu online operation changes as follows: Dedicated LPAR (POWER6): 20-25ms. Shared LPAR (POWER5) : 60-80ms. In both these cases, it was found that the code polls through the loop only once indicating that 1ms is a reasonable value, atleast on pseries. The code needs testing on other powerpc platforms. Signed-off-by:
Gautham R Shenoy <ego@in.ibm.com> Acked-by:
Joel Schopp <jschopp@austin.ibm.com> Signed-off-by:
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Bastian Blank authored
On Thu, Aug 13, 2009 at 04:14:58PM +1000, Benjamin Herrenschmidt wrote: > On Tue, 2009-08-11 at 11:39 +0200, Bastian Blank wrote: > > This patch just disables this driver on SMP kernels, as it is obviously > > not supported. > Why not remove the #error instead ? :-) I don't think it's still > meaningful, especially since we use the timebase for delays nowadays > which doesn't depend on the CPU frequency... Your call. Take this one: The build of a PowerMac 32bit kernel currently fails with error: #warning "WARNING, CPUFREQ not recommended on SMP kernels" Thie patch removes the not longer applicable SMP warning from the PowerMac cpufreq code. Signed-off-by:
Bastian Blank <waldi@debian.org> Signed-off-by:
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Josh Boyer authored
The ptrace POKETEXT interface allows a process to modify the text pages of a child process being ptraced, usually to insert breakpoints via trap instructions. The kernel eventually calls copy_to_user_page, which in turn calls __flush_icache_range to invalidate the icache lines for the child process. However, this function does not work on 44x due to the icache being virtually indexed. This was noticed by a breakpoint being triggered after it had been cleared by ltrace on a 440EPx board. The convenient solution is to do a flash invalidate of the icache in the __flush_icache_range function. Signed-off-by:
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