Commits · a663bf906dce4bfa4d620ecc6b8ac6ef958eb7c2 · linux / linux-davinci

29 Oct, 2005 40 commits

Protect against multiple inclusion. · a663bf90
Ralf Baechle authored Oct 23, 2005
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Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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a663bf90
Remove useless casts of kmalloc return values. · 030274ae
Ralf Baechle authored Oct 21, 2005
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Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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030274ae

Hack to resolve longstanding prefetch issue · e5adb877

Ralf Baechle authored Oct 20, 2005

    
Prefetching may be fatal on some systems if we're prefetching beyond the
end of memory on some systems.  It's also a seriously bad idea on non
dma-coherent systems.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

e5adb877

More foolproofing of the CPU configuration. · 7cf8053b

Ralf Baechle authored Oct 20, 2005

    
Limit the number of cpu type options in the cpu menu to just those
types that are actually available for the select platform.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

7cf8053b

pci-expmem-hack · cb426248

Andrew Isaacson authored Oct 19, 2005

    
CFE 1.2.5 and earlier fails to turn on the ExpMemEn bit in the
PCIFeatureControl register, which means that DMA does not work
beyond physical address 01_0000_0000, ergo to DRAM beyond 1GB.
    
With ExpMemEn turned on, 01_0000_0000-0f_ffff_ffff is mapped,
so DMA works for up to 61 GB of DRAM.
    
Will be fixed in CFE 1.2.6 (yet to be released).
Signed-Off-By: Andy Isaacson <adi@broadcom.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

cb426248

BCM1480 HT support · 8a1417de

Andrew Isaacson authored Oct 19, 2005

    
PCI support code for PLX 7250 PCI-X tunnel on BCM91480B BigSur board.
Signed-Off-By: Andy Isaacson <adi@broadcom.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

8a1417de

Support for the BCM1480 on-chip PCI-X bridge. · dc41f94f

Andrew Isaacson authored Oct 19, 2005

Signed-Off-By: Andy Isaacson <adi@broadcom.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

dc41f94f

SB1 cache exception handling. · a4b5bd9a

Andrew Isaacson authored Oct 19, 2005

    
Expand SB1 cache error handling by adding SB1_CEX_ALWAYS_FATAL and
SB1_CEX_STALL, allowing configurable behavior on cache errors.
Signed-Off-By: Andy Isaacson <adi@broadcom.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

a4b5bd9a

Support for BigSur board. · 9a6dcea1

Andrew Isaacson authored Oct 19, 2005

Signed-Off-By: Andy Isaacson <adi@broadcom.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

9a6dcea1

Add support for BCM1480 family of chips. · f137e463

Andrew Isaacson authored Oct 19, 2005

    
 - Kconfig and Makefile changes
 - arch/mips/sibyte/bcm1480/
 - changes to sibyte common code to support 1480
Signed-Off-By: Andy Isaacson <adi@broadcom.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

f137e463

Add support for SB1A CPU. · 93ce2f52

Andrew Isaacson authored Oct 19, 2005

Signed-Off-By: Andy Isaacson <adi@broadcom.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

93ce2f52

Sibyte header cleanup · 4f19f990

Andrew Isaacson authored Oct 19, 2005

    
Update sibyte headers to match Broadcom internal copies:
 - comment cleanup and updates
 - fix LittleSur part number to match the board silkscreen
Signed-Off-By: Andy Isaacson <adi@broadcom.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

4f19f990

BCM1480 headers · 4cbf2bea

Andrew Isaacson authored Oct 19, 2005

    
Add header files for BCM1480/1280/1455/1255 family of chips, and
update sb1250 headers which are shared by BCM1480 family.
Signed-Off-By: Andy Isaacson <adi@broadcom.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

diff --git a/include/asm-mips/sibyte/bcm1480_int.h b/include/asm-mips/sibyte/bcm1480_int.h
new file mode 100644

4cbf2bea

Sibyte fixes · d121ced2

Andrew Isaacson authored Oct 19, 2005

    
Fix typo in cpu_probe_sibyte.
Signed-Off-By: Andy Isaacson <adi@broadcom.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

d121ced2

Make UL what should be UL. · 485a4a92
Ralf Baechle authored Oct 19, 2005
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Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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485a4a92

Fix zero length sys_cacheflush · 750ccf68

Atsushi Nemoto authored Oct 19, 2005

    
Cacheflush(0, 0, 0) was crashing the system.  This is because
flush_icache_range(start, end) tries to flushing whole address space
(0 - ~0UL) if both start and end are zero.
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

750ccf68

Get 64-bit right in the kgdb stub. · f4c72cc7
Ralf Baechle authored Oct 18, 2005
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Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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f4c72cc7
Sys_lookup_dcookie arguments occupy 4 argument slots. · 0d507d61
Ralf Baechle authored Oct 18, 2005
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Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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0d507d61

FPU emulator garbage collection. · 12616ed2

Ralf Baechle authored Oct 18, 2005

    
First argument of fpu_emulator_cop1Handler() was unused.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

12616ed2

Don't print file name and line in die and die_if_kernel. · 178086c8
Ralf Baechle authored Oct 13, 2005
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Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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178086c8
Rename page argument of flush_cache_page to something more descriptive. · 6ec25809
Ralf Baechle authored Oct 12, 2005
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Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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6ec25809
Define EOWNERDEAD and ENOTRECOVERABLE. · 8f91ed6c
Ralf Baechle authored Oct 09, 2005
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Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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8f91ed6c
Sliceup Kconfig; it's grown too large. · 5e83d430
Ralf Baechle authored Oct 29, 2005
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Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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5e83d430
More configcheck fixes. · beb3ca82
Ralf Baechle authored Oct 29, 2005
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Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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beb3ca82
2.6.14-rc1 updates for MIPS compat types. · 4ee1303a
Ralf Baechle authored Oct 29, 2005
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Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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4ee1303a
Complete the fcntl.h cleanup. · b4f8c423
Ralf Baechle authored Oct 29, 2005
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Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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b4f8c423
Cleanup Sibyte Kconfig a bit further. · 3cd9b680
Ralf Baechle authored Oct 29, 2005
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Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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3cd9b680
Date: Fri Jan 14 03:03:23 2005 +0000 · 9383292f
Ralf Baechle authored Jan 14, 2005
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Locking cleanups.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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9383292f
Fix weirdness in <asm/bug.h> · 8592d4c0
Ralf Baechle authored Oct 29, 2005
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Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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8592d4c0
Fix wrong comment. · dbc57169
Ralf Baechle authored Oct 29, 2005
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Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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dbc57169
Fixup a few lose ends in explicit support for MIPS R1/R2. · ec917c2c
Ralf Baechle authored Oct 07, 2005
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Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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ec917c2c
Document the meaning of the CPU_MIPS32, CPU_MIPS64, CPU_MIPSR1 and · f92c1759
Ralf Baechle authored Oct 07, 2005
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CPU_MIPSR2.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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f92c1759
Protect manipulation of c0_status against preemption and multithreading. · 101b3531
Ralf Baechle authored Oct 06, 2005
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Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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101b3531
Detect 4KSD and treat it like 4KSc. · 8afcb5d8
Ralf Baechle authored Oct 04, 2005
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Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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8afcb5d8
We're no longer hosted on oss for ages ... · d50f7ec9
Ralf Baechle authored Oct 04, 2005
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Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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d50f7ec9
Convert the remaining SPIN_LOCK_UNLOCKED instances to DEFINE_SPINLOCK. · 2f69ddcc
Ralf Baechle authored Oct 03, 2005
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Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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2f69ddcc

Define and initialize kdb_lock using DEFINE_SPINLOCK. · 57468af3

Ralf Baechle authored Oct 03, 2005

Convert kgdb_cpulock into a raw_spinlock_t.
    
SPIN_LOCK_UNLOCKED is deprecated and it's replacement DEFINE_SPINLOCK is
not suitable for arrays of spinlocks.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

57468af3

Make kgdb_wait static. · f8bb3af9

Ralf Baechle authored Oct 03, 2005

    
Nothing outside gdb-stub.c uses kgdb_wait, so change it's definition to
static.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

f8bb3af9

Don't copy SB1 cache error handler to uncached memory. · 65f1f5a2

Ralf Baechle authored Oct 01, 2005

    
This may have made sense on a paranoid day with pass 1 BCM1250 processors
that were throwing cache error exception left and right for no good
reason.  On modern silicion that hardly makes sense and the code had
gotten just an obscurity ...
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

65f1f5a2

Provide 64-bit address space definitions for the Sibyte SB1 CPU core. · 5090dfb5
Ralf Baechle authored Oct 01, 2005
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Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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5090dfb5