- 01 Mar, 2010 3 commits
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Randy Dunlap authored
Fix function prototype to match its actual usage and implementation. drivers/gpu/drm/ttm/ttm_bo_util.c:341:10: error: symbol 'ttm_io_prot' redeclared with different type (originally declared at include/drm/ttm/ttm_bo_driver.h:911) - incompatible argument 1 (different signedness) Signed-off-by: Randy Dunlap <randy.dunlap@oracle.com> Cc: David Airlie <airlied@linux.ie> Signed-off-by: Dave Airlie <airlied@redhat.com>
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Matt Turner authored
Cc: Jerome Glisse <jglisse@redhat.com> Cc: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Corbin Simpson <MostAwesomeDude@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
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Jerome Glisse authored
rs600 asic was missing set_surface_reg callback leading to oops. Signed-off-by: Jerome Glisse <jglisse@redhat.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
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- 25 Feb, 2010 4 commits
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Alex Deucher authored
- add support for pre-avivo chips - add support for fixed post/ref dividers - add support for non-fractional fb dividers By default avivo chips use the new algo and pre-avivo chips use the old algo. Use the "new_pll" module option to toggle between them. Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
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Marek Olšák authored
Signed-off-by: Marek Olšák <maraeo@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
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Jerome Glisse authored
This patch properly set visible VRAM and enforce any pinned buffer to be into visible VRAM. We might later add a flag to release this constraint for some newer hw more clever than previous. Signed-off-by: Jerome Glisse <jglisse@redhat.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
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Alex Deucher authored
cursor x/y are surface relative. fixes fdo bug 26551 Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
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- 22 Feb, 2010 9 commits
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Rafał Miłecki authored
Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
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Rafał Miłecki authored
AtomBIOS tables on non-mobility GPU do not contain POWERSAVE/BATTERY. Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Reviewed-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
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Rafał Miłecki authored
We kept pointers to requested and current clock modes in every power state. That was useless, more /global/ pointers in power struct are enough. Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Reviewed-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
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Alex Deucher authored
- updated swizzle modes for backend map setup - fix programming of a few gfx regs - properly handle pipe/backend setup on LE cards Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
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Alex Deucher authored
This patch fixes occlusion queries and rendering errors on rv740 boards. Hardcoding the backend map is not an optimal solution, but a better fix is being worked on. Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
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Jerome Glisse authored
Version 2 of memory controller did break the initialization for R3XX/R4XX hardware. This patch fix it. Signed-off-by: Jerome Glisse <jglisse@redhat.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
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Dave Airlie authored
This patch adds a check on avivo chips to see if we are in the VBL region for the active crtcs when we trigger the engine change. I appear to have glitches locally on pm transistion (not sure all fixes are in yet) and this at least seems to be correct here, maybe others can test on systems with no glitches.
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Pauli Nieminen authored
Allocation of single large block of memory may fail under memory presure. drm_buffer object can hold one large block of data in multiple independ pages which preents alloation failures. This patch converts all access to command stream to use drm_buffer interface. All direct access to array has to go tough drm_buffer functions to get correct pointer. Outputting the command stream to ring buffer needs to be awear of the split nature of drm_buffer. The output operation requires the new OUT_RING_DRM_BUFFER. Signed-off-by: Pauli Nieminen <suokkos@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
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Pauli Nieminen authored
Allocating multiple pages of memory for data that is coming from user space may fail. To fix memory allocation failures the buffer object should be split to multiple independ pages. drm buffer provides generic interface to copy and process large data arrays from user space. Interface includes allocation and free functions to allocate the buffer object and data storage pages. All access operations are performed relative to a internal pointer which is advanced with drm_buffer_advance function. The buffer can be accessed using drm_buffer_pointer_to_XXX functions if it is known that requested object doesn't split over a page boundary. These functions don't do any error checking to maximize performance. If there is large object which could be split there is special drm_buffer_read_object function. drm_buffer_read_object takes a pointer as argument which is used as temporary store for data if it is split over boundary in the buffer. Signed-off-by: Pauli Nieminen <suokkos@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
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- 18 Feb, 2010 10 commits
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Jerome Glisse authored
Get rid of _location and use _start/_end also simplify the computation of vram_start|end & gtt_start|end. For R1XX-R2XX we place VRAM at the same address of PCI aperture, those GPU shouldn't have much memory and seems to behave better when setup that way. For R3XX and newer we place VRAM at 0. For R6XX-R7XX AGP we place VRAM before or after AGP aperture this might limit to limit the VRAM size but it's very unlikely. For IGP we don't change the VRAM placement. Tested on (compiz,quake3,suspend/resume): PCI/PCIE:RV280,R420,RV515,RV570,RV610,RV710 AGP:RV100,RV280,R420,RV350,RV620(RPB*),RV730 IGP:RS480(RPB*),RS690,RS780(RPB*),RS880 RPB: resume previously broken V2 correct commit message to reflect more accurately the bug and move VRAM placement to 0 for most of the GPU to avoid limiting VRAM. Signed-off-by: Jerome Glisse <jglisse@redhat.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
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Pauli Nieminen authored
r200 cards have dma engine which can be used to tranfer data between vram and system memory. r300 dma engine registers match r200 dma engine. Enabling dma copy for r200 is simple as hooking r200 asic to already existing function r300_copy_dma. Rename r300_dma_copy to r200_dma_copyto reflect that supports starts from r200 cards. v2: Created a new asic object for r200 cards. Signed-off-by: Pauli Nieminen <suokkos@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
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Pauli Nieminen authored
Setting global asic structure to point to different function would cause problem in system where is multiple r300 cards with different bus type. r300_asic_pcie is just copy from r300_asic with gart tlb functions replaced with pcie versions. Signed-off-by: Pauli Nieminen <suokkos@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
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Alex Deucher authored
r6xx/r7xx use the rs600 variant. This old one just confuses things. Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
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Alex Deucher authored
r600_ioctl_wait_idle() now handles this. v2: update blit fence counts Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
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Alex Deucher authored
fixes fdo bug 26358 Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
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Rafał Miłecki authored
Signed-off-by: Dave Airlie <airlied@redhat.com>
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Rafał Miłecki authored
Fixes fdo bug #26329 Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Tested-by: Tobias Jakobi <liquid.acid@gmx.net> Signed-off-by: Dave Airlie <airlied@redhat.com>
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Rafał Miłecki authored
We should stop audio-state-reading timer before we turn off engine Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
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Alex Deucher authored
drivers/gpu/drm/radeon/r600_cs.c: In function ‘r600_cs_track_check’: drivers/gpu/drm/radeon/r600_cs.c:166: warning: ‘bpe’ may be used uninitialized in this function drivers/gpu/drm/radeon/r600_cs.c:166: note: ‘bpe’ was declared here drivers/gpu/drm/radeon/r600_cs.c: In function ‘r600_cs_parse’: drivers/gpu/drm/radeon/r600_cs.c:938: warning: ‘bpe’ may be used uninitialized in this function drivers/gpu/drm/radeon/r600_cs.c:938: note: ‘bpe’ was declared here Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
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- 15 Feb, 2010 3 commits
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Jerome Glisse authored
Previous code did associate fence to bo before the fence was emited and it also didn't lock protected access to ttm sync_obj member. Both of this flaw leads to possible race between different code path. This patch fix this by associating fence only once the fence is emitted and properly lock protect access to sync_obj member of ttm. Fix: https://bugs.freedesktop.org/show_bug.cgi?id=26438 and likely similar others bugs Signed-off-by: Jerome Glisse <jglisse@redhat.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
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Jerome Glisse authored
There is 3 different distinct states for an indirect buffer (IB) : 1- free with no fence 2- free with a fence 3- non free (fence doesn't matter) Previous code mixed case 2 & 3 in a single one leading to possible catastrophique failure. This patch rework the handling and properly separate each case. So when you get ib we set the ib as non free and fence status doesn't matter. Fence become active (ie has a meaning for the ib code) once the ib is scheduled or free. This patch also get rid of the alloc bitmap as it was overkill, we know go through IB pool list like in a ring buffer as the oldest IB is the first one the will be free. Fix : https://bugs.freedesktop.org/show_bug.cgi?id=26438 and likely other bugs. V2 remove the scheduled list, it's useless now, fix free ib scanning Signed-off-by: Jerome Glisse <jglisse@redhat.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
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Dave Airlie authored
Suggested by Alex Deucher @ AMD Signed-off-by: Dave Airlie <airlied@redhat.com>
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- 11 Feb, 2010 9 commits
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Jerome Glisse authored
radeon_cs kfree the tracker structure but for r6xx/r7xx we want to kfree it inside the parse function because we share it with the UMS code path. Set tracker to NULL after freeing it will avoid double free. Signed-off-by: Jerome Glisse <jglisse@redhat.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
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Dave Airlie authored
this uses a new entrypoint to invalidate gart entries instead of using 0. Changed to rather than pointing to 0 address point empty entry to dummy page. This might help to avoid hard lockup if for some wrong reasons GPU try to access unmapped GART entry. I'm not 100% sure this is going to work, we probably need to allocate a dummy page and point all the GTT entries at it similiar to what AGP does. but we can test this first I suppose. Signed-off-by: Jerome Glisse <jglisse@redhat.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
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Dave Airlie authored
stops us trying to treat a OF rom as a PCI rom. Signed-off-by: Dave Airlie <airlied@redhat.com>
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Michel Dänzer authored
It's happened time and time again (most recently with the support for EDID hardcoded in the BIOS ROM) that new code didn't check for rdev->bios being non-NULL before triggering dereferences of it. This would result in an oops/panic on setups with no BIOS ROM. Hopefully this central test will be more robust. Signed-off-by: Michel Dänzer <daenzer@vmware.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
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Jerome Glisse authored
This patch add cs checker to r600/r700 hw. Command stream checking will rewrite some of the cs value in order to restrict GPU access to BO size. This doesn't break old userspace but just enforce safe value. It should break any things that was using the r600/r700 cs ioctl to do forbidden things (malicious software), though we are not aware of such things. Here is the list of thing we check : - enforcing resource size - enforcing color buffer slice tile max, will restrict cb access - enforcing db buffer slice tile max, will restrict db access We don't check for shader bigger than the BO in which they are supposed to be, such use would lead to GPU lockup and is harmless from security POV, as far as we can tell (note that even checking for this wouldn't prevent someone to write bogus shader that lead to lockup). This patch has received as much testing as humanly possible with old userspace to check that it didn't break such configuration. However not all the applications out there were tested, thus it might broke some odd, rare applications. [airlied: fix rules for cs checker for parallel builds] Signed-off-by: Jerome Glisse <jglisse@redhat.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
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Alex Deucher authored
original evergreen patches we against a kernel tree without my radeon i2c algo changes. Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
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Alex Deucher authored
Fix a typo in crtc offset setup that set the crtc instances wrong for all crtcs except the first. Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
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Alex Deucher authored
Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
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Alex Deucher authored
Pre-pcie chips seem to use the reference clock rather than the sclk. Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
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- 08 Feb, 2010 2 commits
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Alex Deucher authored
This adds initial Evergreen KMS support, it doesn't include any acceleration features or interrupt handling yet. Major changes are DCE4 handling for PLLs for the > 2 crtcs. Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
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Alex Deucher authored
This merges ugly whitespace we want to keep for consistency along with the latest upstream changes. Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
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