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  1. 08 Nov, 2009 2 commits
    • Lennert Buytenhek's avatar
      [ARM] Kirkwood: clarify PCIe MEM bus/physical address distinction · a1897fa6
      Lennert Buytenhek authored 
      Signed-off-by: default avatarLennert Buytenhek <buytenh@marvell.com>
Signed-off-by: default avatarNicolas Pitre <nico@marvell.com>
      a1897fa6
    • Lennert Buytenhek's avatar
      [ARM] kirkwood: fix PCI I/O port assignment · 35f029e2
      Lennert Buytenhek authored 
      Instead of allocating PCI devices I/O port bus addresses from the
000xxxxx I/O port range as intended, due to a bus versus physical
address mixup, the Kirkwood PCIe handling code inadvertently
allocated I/O port bus addresses from the f20xxxxx address range
(which is the physical address range of the PCIe I/O mapping window),
but then direct all I/O port accesses to bus addresses 000xxxxx,
which would then not be decoded at all.

Fix this by setting the base address of the PCIe I/O space struct
resource to KIRKWOOD_PCIE_IO_BUS_BASE instead of the incorrect
KIRKWOOD_PCIE_IO_PHYS_BASE, and fix up __io() to expect addresses
offsetted by the former instead of the latter.

(The suggested fix of directing I/O port accesses from the host to
bus addresses f20xxxxx instead has the problem that assigning full
32bit I/O port bus addresses (f20xxxxx) doesn't work on all PCI
devices, as not all PCI devices implement full 32 bit BAR registers
for I/O ports.  We should really try to allocate I/O port bus
addresses that fit in 16 bits.)
Signed-off-by: default avatarLennert Buytenhek <buytenh@marvell.com>
Signed-off-by: default avatarNicolas Pitre <nico@marvell.com>
      35f029e2
  3. 06 Nov, 2009 3 commits
  5. 03 Nov, 2009 26 commits
  7. 02 Nov, 2009 9 commits