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  1. 17 Sep, 2009 5 commits
  3. 11 Sep, 2009 3 commits
    • Chris Wilson's avatar
      drm/i915: Only destroy a constructed mmap offset · 7e616158
      Chris Wilson authored 
      drm_ht_remove_item() does not handle removing an absent item and the hlist
in particular is incorrectly initialised. The easy remedy is simply skip
calling i915_gem_free_mmap_offset() unless we have actually created the
offset and associated ht entry.

This also fixes the mishandling of a partially constructed offset which
leaves pointers initialized after freeing them along the
i915_gem_create_mmap_offset() error paths.

In particular this should fix the oops found here:
https://bugs.launchpad.net/ubuntu/+source/xserver-xorg-video-intel/+bug/415357/comments/8Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: default avatarEric Anholt <eric@anholt.net>
Cc: stable@kernel.org
      7e616158
    • Eric Anholt's avatar
      agp/intel: Fix the pre-9xx chipset flush. · e517a5e9
      Eric Anholt authored 
      Ever since we enabled GEM, the pre-9xx chipsets (particularly 865) have had
serious stability issues.  Back in May a wbinvd was added to the DRM to
work around much of the problem.  Some failure remained -- easily visible
by dragging a window around on an X -retro desktop, or by looking at bugzilla.

The chipset flush was on the right track -- hitting the right amount of
memory, and it appears to be the only way to flush on these chipsets, but the
flush page was mapped uncached.  As a result, the writes trying to clear the
writeback cache ended up bypassing the cache, and not flushing anything!  The
wbinvd would flush out other writeback data and often cause the data we wanted
to get flushed, but not always.  By removing the setting of the page to UC
and instead just clflushing the data we write to try to flush it, we get the
desired behavior with no wbinvd.

This exports clflush_cache_range(), which was laying around and happened to
basically match the code I was otherwise going to copy from the DRM.
Signed-off-by: default avatarEric Anholt <eric@anholt.net>
Signed-off-by: default avatarBrice Goglin <Brice.Goglin@ens-lyon.org>
Cc: stable@kernel.org
      e517a5e9
    • Jesse Barnes's avatar
      drm/i915: framebuffer compression for pre-GM45 · 80824003
      Jesse Barnes authored 
      This patch adds framebuffer compression (good for about ~0.5W power
savings in the best case) support for pre-GM45 chips.  GM45+ have a new,
more flexible FBC scheme that will be added in a separate patch.

FBC can't always be enabled: the compressed buffer must be physically
contiguous and reside in stolen space.  So if you have a large display
and a small amount of stolen memory, you may not be able to take
advantage of FBC.  In some cases, a BIOS setting controls how much
stolen space is available.  Increasing this to 8 or 16M can help.
Signed-off-by: default avatarJesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: default avatarEric Anholt <eric@anholt.net>
      80824003
  5. 10 Sep, 2009 9 commits
  7. 09 Sep, 2009 3 commits
  9. 08 Sep, 2009 12 commits
  11. 07 Sep, 2009 8 commits