- 17 Apr, 2008 40 commits
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Alexey Starikovskiy authored
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Alexey Starikovskiy <astarikovskiy@suse.de> Signed-off-by:
Ingo Molnar <mingo@elte.hu>
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Alexey Starikovskiy authored
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Alexey Starikovskiy authored
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Alexey Starikovskiy authored
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Alexey Starikovskiy authored
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Alexey Starikovskiy authored
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Alexey Starikovskiy authored
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Alexey Starikovskiy authored
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Alexey Starikovskiy authored
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Alexey Starikovskiy authored
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Alexey Starikovskiy authored
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Alexey Starikovskiy authored
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Alexey Starikovskiy authored
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Alexey Starikovskiy authored
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Alexey Starikovskiy authored
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Alexey Starikovskiy authored
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Alexey Starikovskiy authored
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Alexey Starikovskiy authored
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Alexey Starikovskiy authored
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Alexey Starikovskiy authored
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Alexey Starikovskiy authored
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Ingo Molnar authored
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Alexey Starikovskiy authored
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Alexey Starikovskiy authored
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Alexey Starikovskiy authored
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Alexey Starikovskiy authored
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Alexey Starikovskiy authored
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Alexey Starikovskiy authored
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Ingo Molnar authored
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Randy Dunlap authored
without this patch: VOYAGER: kernel/built-in.o: In function `crash_kexec': (.text+0x28588): undefined reference to `machine_crash_shutdown' VISWS: kernel/built-in.o: In function `crash_kexec': /next-20080401/kernel/kexec.c:1074: undefined reference to `machine_crash_shutdown' make[1]: *** [.tmp_vmlinux1] Error 1 because arch/x86/kernel/reboot.c isn't built since CONFIG_X86_BIOS_REBOOT=n, so machine_crash_shutdown() isn't available. This patch does seem a small bit odd since the KEXEC help text says that kexec is independent of the system firmware. Signed-off-by:
Randy Dunlap <randy.dunlap@oracle.com> Cc: Eric Biederman <ebiederm@xmission.com> Cc: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by:
Andrew Morton <akpm@linux-foundation.org> Signed-off-by:
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Hugh Dickins authored
I've now noticed that the machine I call MPENTIUM4 for 32-bit kernels is called MPSC for 64-bit kernels, and in that case it still doesn't get the P6 NOPs it ought to. hpa explains that MK8 should still be excluded, so it's just a matter of including MPSC along with MPENTIUM4. Signed-off-by:
Hugh Dickins <hugh@veritas.com> Acked-by:
H. Peter Anvin <hpa@zytor.com> Signed-off-by:
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Cyrill Gorcunov authored
We should call for kfree if only we really need it. Though it's safe to call kfree with NULL pointer passed in this code we've already tested the pointer and can eliminate the call Signed-off-by:
Cyrill Gorcunov <gorcunov@gmail.com> Signed-off-by:
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Ingo Molnar authored
use of the bzImage symlinks in developer scripts is still widespread, so lets extend the removal period by 2 years. These symlinks cost us near nothing. Signed-off-by: -
Ingo Molnar authored
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Jack Steiner authored
Yinghai Lu pointed out a bug in the previous patches, fix double-shift of apicid. Signed-off-by:
Jack Steiner <steiner@sgi.com> Signed-off-by:
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Ingo Molnar authored
Peter Zijlstra pointed out that it's unused. Signed-off-by: -
Mike Travis authored
Cleanup references to the early cpu maps for the non-SMP configuration and remove some functions called for SMP configurations only. Cc: Andi Kleen <ak@suse.de> Cc: Christoph Lameter <clameter@sgi.com> Signed-off-by:
Mike Travis <travis@sgi.com> Signed-off-by:
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Ingo Molnar authored
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Jack Steiner authored
UV supports really big systems. So big, in fact, that the APICID register does not contain enough bits to contain an APICID that is unique across all cpus. The UV BIOS supports 3 APICID modes: - legacy mode. This mode uses the old APIC mode where APICID is in bits [31:24] of the APICID register. - x2apic mode. This mode is whitebox-compatible. APICIDs are unique across all cpus. Standard x2apic APIC operations (Intel-defined) can be used for IPIs. The node identifier fits within the Intel-defined portion of the APICID register. - x2apic-uv mode. In this mode, the APICIDs on each node have unique IDs, but IDs on different node are not unique. For example, if each mode has 32 cpus, the APICIDs on each node might be 0 - 31. Every node has the same set of IDs. The UV hub is used to route IPIs/interrupts to the correct node. Traditional APIC operations WILL NOT WORK. In x2apic-uv mode, the ACPI tables all contain a full unique ID (note: exact bit layout still changing but the following is close): nnnnnnnnnnlc0cch n = unique node number l = socket number on board c = core h = hyperthread Only the "lc0cch" bits are written to the APICID register. The remaining bits are supplied by having the get_apic_id() function "OR" the extra bits into the value read from the APICID register. (Hmmm.. why not keep the ENTIRE APICID register in per-cpu data....) The x2apic-uv mode is recognized by the MADT table containing: oem_id = "SGI" oem_table_id = "UV-X" Signed-off-by:
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Ingo Molnar authored
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