- 12 Sep, 2005 40 commits
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Andi Kleen authored
Since this is shared code I had to implement it for i386 too Signed-off-by:
Andi Kleen <ak@suse.de> Signed-off-by:
Linus Torvalds <torvalds@osdl.org>
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Andi Kleen authored
The resume code uses CPU hotplug now so at resume time we only ever see one CPU. Pointed out by Yu Luming. Signed-off-by:
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Andi Kleen authored
The FLATMEM people added it, but there doesn't seem a good reason because end_pfn is identical. Signed-off-by:
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Andi Kleen authored
Avoids a very dumb loop Signed-off-by:
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Andi Kleen authored
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Andi Kleen authored
Use pcibus_to_node directly Signed-off-by:
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Andi Kleen authored
It could be wrong for kexec or other cases. Read it from the CPU instead. Signed-off-by:
Murali <muralim@in.ibm.com> Signed-off-by:
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Andi Kleen authored
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Andi Kleen authored
One machine is constantly throwing NMI watchdog timeouts in mce_log This was one attempt to fix it. (AK: this doesn't actually fix the bug I'm seeing unfortunately, probably drop. I don't like it that the reader can spin forever now waiting for a writer) Signed-off-by:
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Andi Kleen authored
It's already handled in the main swiotlb code. Signed-off-by:
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Andi Kleen authored
No-one needs it then Signed-off-by:
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Andi Kleen authored
This leads to bootmem allocating first from node 0 instead of from the last node. This avoids swiotlb allocating on the last node, which doesn't really work on a machine with >4GB. Note: there is a better patch around from someone else that gets rid of the pgdat list completely. Signed-off-by:
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Andi Kleen authored
PCI_DMA_BUS_IS_PHYS has to be zero even when the GART IOMMU is disabled and the swiotlb is used. Otherwise the block layer does unnecessary double bouncing. Signed-off-by:
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Andi Kleen authored
Originally from Stuart Hayes. When setting up the APIC for the Uniprocessor kernel don't assume the CPU has an APIC ID of zero. This fixes boot with the UP kernel on Dell PowerEdge 6800/6850 4way systems. Cc: Stuart.Hayes@dell.com Signed-off-by:
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Andi Kleen authored
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Andi Kleen authored
In particular on systems where the local APIC space and node space is very different from the Linux CPU number space. Previously the older NUMA setup code directly parsing the K8 northbridge registers had some issues on 8 socket or dual core systems. This patch fixes them. This is mainly done by fixing some confusion between Linux CPU numbers and local APIC ids. We now pass the local APIC IDs to later code, which avoids mismatches. Also add some heuristics to detect cases where the Hypertransport nodeids and the local APIC IDs don't match, but are shifted by a constant offset. This is still all quite hackish, hopefully BIOS writers fill in correct SRATs instead. Signed-off-by:
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Andi Kleen authored
Suggested by someone I forgot who sorry. Signed-off-by:
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Andi Kleen authored
Signed-off-by:
Suresh Sidda <suresh.b.siddha@intel.com> Signed-off-by:
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Andi Kleen authored
Do that later when the CPU boots. SRAT just stores the APIC<->Node mapping node. This fixes problems on systems where the order of SRAT entries does not match the MADT. Signed-off-by:
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Andi Kleen authored
No functional changes Signed-off-by:
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Andi Kleen authored
We used to disable them to work around a bug, but that is not needed anymore. Keeping them enabled avoids the NMI watchdog triggering in some cases. Signed-off-by:
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Andi Kleen authored
Handles case where BIOS gives CPUs very large APIC numbers correctly. Signed-off-by:
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Andi Kleen authored
No x86-64 chipset has these APICs. Signed-off-by:
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Andi Kleen authored
This was just needed for the Numasaurus, which fortunately doesn't support x86-64 CPUs. Signed-off-by:
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Andi Kleen authored
No x86-64 chipset has this bug Generated code doesn't change because it was always disabled. Signed-off-by:
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Andi Kleen authored
We don't do workarounds for ancient hardware bugs. Signed-off-by:
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Andi Kleen authored
Allow diskless booting. Signed-off-by:
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Andi Kleen authored
Now that Greg implemented MCFG/_SEG support this shouldn't be needed anymore Cc: gregkh@suse.de Signed-off-by:
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Paul Jackson authored
Optimize the deadlock avoidance check on the global cpuset semaphore cpuset_sem. Instead of adding a depth counter to the task struct of each task, rather just two words are enough, one to store the depth and the other the current cpuset_sem holder. Thanks to Nikita Danilov for the idea. Signed-off-by:
Paul Jackson <pj@sgi.com> [ We may want to change this further, but at least it's now a totally internal decision to the cpusets code ] Signed-off-by:
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Evgeniy Polyakov authored
Remove w1 comments from crc16.h and move specific constants into w1_ds2433.c where they are used. Replace %d with %zd. Signed-off-by:
Evgeniy Polyakov <johnpol@2ka.mipt.ru> Signed-off-by:
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Linus Torvalds authored
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Linus Torvalds authored
..and only enable them for ia64. The functions are only valid when the whole system has been totally stopped and no scheduler activity is ongoing on any CPU, and interrupts are globally disabled. In other words, they aren't useful for anything else. So make sure that nobody can use them by mistake. Signed-off-by: -
Roland McGrath authored
Signed-off-by:
Roland McGrath <roland@redhat.com> Acked-by:
Atsushi Nemoto <anemo@mba.ocn.ne.jp> Acked-by:
Ingo Molnar <mingo@elte.hu> Signed-off-by:
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Anton Blanchard authored
ppc64_attention_msg and ppc64_dump_msg are not used so remove them. Signed-off-by:
Anton Blanchard <anton@samba.org> Signed-off-by:
Paul Mackerras <paulus@samba.org>
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Anton Blanchard authored
If the rtas start-cpu token doesnt exist then presume the cpu is already spinning. If it isnt we will catch it later on when the cpu doesnt respond. Signed-off-by:
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Anton Blanchard authored
Fix up some badly indented code. Signed-off-by:
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Anton Blanchard authored
A few xics cleanups: - Make some things static. - Be more consistent with error printing - interrupts are unsigned, error values are signed. Signed-off-by:
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Anton Blanchard authored
Add hardware data breakpoint support. Signed-off-by:
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Anton Blanchard authored
- Add PTRACE_GET_DEBUGREG/PTRACE_SET_DEBUGREG. The definition is as follows: /* * Get or set a debug register. The first 16 are DABR registers and the * second 16 are IABR registers. */ #define PTRACE_GET_DEBUGREG 25 #define PTRACE_SET_DEBUGREG 26 DABR == data breakpoint and IABR = instruction breakpoint in IBM speak. We could split out the IABR into 2 more ptrace calls but I figured there was no need and 16 DABR registers should be more than enough (POWER4/POWER5 have one). - Add 2 new SIGTRAP si_codes: TRAP_HWBKPT and TRAP_BRANCH. I couldnt find any standards on either of these so I copied what ia64 is doing. Again this might be better placed in include/asm-generic/siginfo.h Signed-off-by:
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Anton Blanchard authored
Fix up some whitespace issues in ptrace32.c Signed-off-by:
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