- 11 Apr, 2008 31 commits
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Paul Walmsley authored
Add non-CORE DPLL rate set code and M,N programming for OMAP3. Connect it to OMAP34xx DPLLs 1, 2, 4, 5 via the clock framework. You may see some warnings on rate sets from the freqsel code. The table that TI presented in the 3430 TRM Rev F does not cover Fint < 750000, which definitely occurs in practice. However, the lack of this freqsel case does not appear to impair the DPLL rate change. Signed-off-by:
Paul Walmsley <paul@pwsan.com> Signed-off-by:
Tony Lindgren <tony@atomide.com>
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Paul Walmsley authored
This patch adds a new rate rounding algorithm for DPLL clocks on the OMAP2/3 architecture. For a desired DPLL target rate, there may be several multiplier/divider (M, N) values which will generate a sufficiently close rate. Lower N values result in greater power economy. However, lower N values can cause the difference between the rounded rate and the target rate ("rate error") to be larger than it would be with a higher N. This can cause downstream devices to run more slowly than they otherwise would. This DPLL rate rounding algorithm: - attempts to find the lowest possible N (DPLL divider) to reach the target_rate (since, according to Richard Woodruff <r-woodruff@ti.com>, lower N values save more power than higher N values). - allows developers to set an upper bound on the error between the rounded rate and the desired target rate ("rate tolerance"), so an appropriate balance between rate fidelity and power savings can be set. This maximum rate error tolerance is set via omap2_set_dpll_rate_tolerance(). - never returns a rounded rate higher than the target rate. The rate rounding algorithm caches the last rounded M, N, and rate computation to avoid rounding the rate twice for each clk_set_rate() call. (This patch does not yet implement set_rate for DPLLs; that follows in a future patch.) The algorithm trades execution speed for rate accuracy. It will find the (M, N) set that results in the least rate error, within a specified rate tolerance. It does this by evaluating each divider setting - on OMAP3, this involves 128 steps. Another approach to DPLL rate rounding would be to bail out as soon as a valid rate is found within the rate tolerance, which would trade rate accuracy for execution speed. Alternate implementations welcome. This code is not yet used by the OMAP24XX DPLL clock, since it is currently defined as a composite clock, fusing the DPLL M,N and the M2 output divider. This patch also renames the existing OMAP24xx DPLL programming functions to highlight that they program both the DPLL and the DPLL's output multiplier. Signed-off-by: -
Mikko Ylinen authored
Put madc driver into kbuild. Signed-off-by:
Mikko Ylinen <mikko.k.ylinen@nokia.com> Updated help text on Kconfig for TWL4030 MADC driver. Signed-off-by:
Felipe Balbi <felipe.balbi@nokia.com> Signed-off-by:
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Mikko Ylinen authored
Introduce twl4030 madc driver. Signed-off-by:
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Felipe Balbi authored
TWL4030's Kconfig entries was a bit mixed. Fix some missing '\n' Add missing space in two-lined printks Signed-off-by:
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Felipe Balbi authored
twl4030_i2c_write_u8 expects a u8 variable. Change ctrl to be u8 in power_companion_init(). Signed-off-by:
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Felipe Balbi authored
Get rid of some sparse warnings in twl4030 driver. Signed-off-by:
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Felipe Balbi authored
Get rid of some sparse warnings in musb_hdrc driver. Signed-off-by:
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Felipe Balbi authored
Misc cleanup patch. Signed-off-by:
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Felipe Balbi authored
Misc cleanup patch. Signed-off-by:
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Felipe Balbi authored
Misc cleanup patch. Signed-off-by:
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Felipe Balbi authored
Misc cleanup patch. Signed-off-by:
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Felipe Balbi authored
Misc cleanup patch. Signed-off-by:
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Felipe Balbi authored
Misc cleanup patch. Signed-off-by:
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Felipe Balbi authored
Misc cleanup patch. Signed-off-by:
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Felipe Balbi authored
Misc cleanup patch. Signed-off-by:
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Felipe Balbi authored
Misc cleanup patch. Signed-off-by:
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Felipe Balbi authored
Misc cleanup patch. Signed-off-by:
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Felipe Balbi authored
Misc cleanup patch. Signed-off-by:
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Felipe Balbi authored
Misc cleanup patch. Signed-off-by:
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Felipe Balbi authored
Misc cleanup patch. Signed-off-by:
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Felipe Balbi authored
Misc cleanup patch. Signed-off-by:
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Felipe Balbi authored
Misc cleanup patch. Signed-off-by:
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Felipe Balbi authored
Misc cleanup patch. Signed-off-by:
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Felipe Balbi authored
Misc cleanup patch. Signed-off-by:
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Felipe Balbi authored
Misc cleanup patch. Signed-off-by:
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Felipe Balbi authored
Misc cleanup patch. Signed-off-by:
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Felipe Balbi authored
Misc cleanup patch. Signed-off-by:
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Felipe Balbi authored
Misc cleanup patch. Signed-off-by:
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Felipe Balbi authored
Misc cleanup patch. Signed-off-by:
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Felipe Balbi authored
Misc cleanup patch. Signed-off-by:
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- 10 Apr, 2008 2 commits
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Tony Lindgren authored
Remove cm_write_reg(), cm_read_reg(), prm_write_reg(), prm_read_reg() and replace them with __raw_readl() and __raw_writel(). Based on comments from RMK. Signed-off-by: -
Tony Lindgren authored
Call clk_enable() before clk_get_rate(). Also free use gpmc_clk instead of it's parent l3 clock. Fixes based on comments from RMK, the real fix would be to use the gpmc functions for timing calculations. Signed-off-by:
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- 09 Apr, 2008 1 commit
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Carlos Eduardo Aguiar authored
This patch adds missing defines for TWL4030. Signed-off-by:
Francisco Alecrim <francisco.alecrim@indt.org.br> Signed-off-by:
Carlos Eduardo Aguiar <carlos.aguiar@indt.org.br> Acked-by:
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- 04 Apr, 2008 6 commits
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tapio laxström authored
Signed-off-by:
tapio laxström <ext-tapio.laxstroem@nokia.com> Signed-off-by:
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Paul Walmsley authored
This patch implements enable/disable for non-CORE DPLLs (DPLLs 1, 2, 4, 5) in the OMAP34xx clock framework. "Enabling" a DPLL in this context means taking the DPLL from off to lock, off to bypass, or bypass to lock. If the clock's target rate is set to the DPLL parent's clock rate, the DPLL will go to bypass. Otherwise, the DPLL will attempt to lock. "Disabling" means going from bypass or lock to off. Jouni Högander contributed a fix for _omap3_noncore_dpll_lock().to bypass the DPLL state test when the DPLL is in autoidle mode. Signed-off-by:
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Paul Walmsley authored
This patch adds support for DPLL autoidle control to the OMAP3 clock framework. These functions will be used by the noncore DPLL enable and disable code - this is because, according to the CDP code, the DPLL autoidle status must be saved and restored across DPLL lock/bypass/off transitions. N.B.: the CORE DPLL (DPLL3) has three autoidle mode options, rather than just two. This code currently does not support the third option, low-power bypass autoidle. Signed-off-by:
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Paul Walmsley authored
Ensure that people who have contributed several bug fixes to the 34xx clock framework are appropriately credited. Signed-off-by:
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Paul Walmsley authored
Convert existing code that reads, modifies, and writes back CM/PRM register values to use the rmw functions introduced in the previous patch. This code should eventually disappear once clockdomain handling is integrated into the 24xx clock framework. Also restructure arch/arm/mach-omap2/prcm.c slightly while we are here. Signed-off-by:
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Paul Walmsley authored
This patch implements an idea from Igor Stoppa <igor.stoppa@nokia.com> from last year. We use functions to modify PRM/CM register bits, rather than open-coding those operations. The patch provides functions that do read + AND + OR + write sequences on CM and PRM registers: {cm,prm}_rmw_reg_bits(), and {cm,prm}_rmw_mod_reg_bits(). Several convenience functions are then implemented on top of those functions for setting and clearing bits: {cm,prm}_{set,clear}_mod_reg_bits(). These functions don't provide any locking; it is expected that the caller will handle this. Thanks to Jouni Högander <jouni.hogander@nokia.com> for catching some embarrassing errors in earlier versions of this code. Signed-off-by:
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