- 12 Jan, 2006 40 commits
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Ravikiran G Thirumalai authored
vSMP specific alignment patch to 1. Define INTERNODE_CACHE_SHIFT for vSMP 2. Use this for alignment of critical structures 3. Use INTERNODE_CACHE_SHIFT for ARCH_MIN_TASKALIGN, and let the slab align task_struct allocations to the internode cacheline size 4. Introduce and use ARCH_MIN_MMSTRUCT_ALIGN for mm_struct slab allocations. Signed-off-by:
Ravikiran Thirumalai <kiran@scalemp.com> Signed-off-by:
Shai Fultheim <shai@scalemp.com> Signed-off-by:
Andi Kleen <ak@suse.de> Signed-off-by:
Linus Torvalds <torvalds@osdl.org>
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Andi Kleen authored
Fixes CC fs/nfsctl.o In file included from include2/asm/atomic.h:427, from /home/lsrc/quilt/linux/include/linux/file.h:8, from /home/lsrc/quilt/linux/fs/nfsctl.c:8: /home/lsrc/quilt/linux/include/asm-generic/atomic.h:20:5: warning: "BITS_PER_LONG" is not defined Signed-off-by: -
Brian Gerst authored
Move the #ifdef into the function body. Signed-off-by:
Brian Gerst <bgerst@didntduck.org> Signed-off-by:
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Eric W. Biederman authored
Currently we attempt to restore virtual wire mode on reboot, which only works if we can figure out where the i8259 is connected. This is very useful when we are kexec another kernel and likely helpful to an peculiar BIOS that make assumptions about how the system is setup. Since the acpi MADT table does not provide the location where the i8259 is connected we have to look at the hardware to figure it out. Most systems have the i8259 connected the local apic of the cpu so won't be affected but people running Opteron and some serverworks chipsets should be able to use kexec now. In addition this patch removes the hard coded assumption that the io_apic that delivers isa interrups is always known to the kernel as io_apic 0. There does not appear to be anything to guarantee that assumption is true. And From: Vivek Goyal <vgoyal@in.ibm.com> A minor fix to the patch which remembers the location of where i8259 is connected. Now counter i has been replaced by apic. counter i is having some junk value which was leading to non-detection of i8259 connected to IOAPIC. Signed-off-by:
Eric W. Biederman <ebiederm@xmission.com> Signed-off-by:
Vivek Goyal <vgoyal@in.ibm.com> Signed-off-by:
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Chuck Ebbert authored
Setting RF (resume flag) allows a debugger to resume execution after a code breakpoint without tripping the breakpoint again. It is reset by the CPU after executing one instruction. Signed-off-by:
Chuck Ebbert <76306.1226@compuserve.com> Signed-off-by:
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Chuck Ebbert authored
The manual says Int 6 is "invalid opcode", not "invalid operand". Signed-off-by:
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Luiz Fernando Capitulino authored
Fixes the following sparse warnings: arch/x86_64/kernel/mce_amd.c:321:29: warning: Using plain integer as NULL pointer arch/x86_64/kernel/mce_amd.c:410:41: warning: Using plain integer as NULL pointer Signed-off-by:
Luiz Capitulino <lcapitulino@mandriva.com.br> Signed-off-by:
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Andi Kleen authored
It was set as an NMI, but the NMI bit always forces an interrupt to end up at vector 2. So it was never used. Remove. Signed-off-by:
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Jason Uhlenkott authored
It looks like the new scalable TLB flush code for x86_64 is claiming one more IRQ vector than it actually uses. Signed-off-by:
Jason Uhlenkott <jasonuhl@sgi.com> Signed-off-by:
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Andi Kleen authored
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Andi Kleen authored
Fix CC arch/x86_64/kernel/nmi.o linux/arch/x86_64/kernel/nmi.c: In function ???check_nmi_watchdog???: linux/arch/x86_64/kernel/nmi.c:155: warning: statement with no effect on Uniprocessor builds. Signed-off-by:
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Ravikiran G Thirumalai authored
Patch uses a static PDA array early at boot and reallocates processor PDA with node local memory when kmalloc is ready, just before pda_init. The boot_cpu_pda is needed since the cpu_pda is used even before pda_init for that cpu is called (to set the static per-cpu areas offset table etc) Signed-off-by:
Ravikiran Thirumalai <kiran@scalex86.org> Signed-off-by:
Shai Fultheim <shai@scalex86.org> Signed-off-by:
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Ravikiran G Thirumalai authored
Helper patch to change cpu_pda users to use macros to access cpu_pda instead of the cpu_pda[] array. Signed-off-by:
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Ravikiran Thirumalai authored
Patch enables early intialization of cpu_to_node. apicid_to_node is built by reading the SRAT table, from acpi_numa_init with ACPI_NUMA and k8_scan_nodes with K8_NUMA. x86_cpu_to_apicid is built by parsing the ACPI MADT table, from acpi_boot_init. We combine these two tables and setup cpu_to_node. Early intialization helps the static per_cpu_areas in getting pages from correct node. Change since last release: Do not initialize early init_cpu_to_node for faking node cases. Patch tested on TYAN dual core 4P board with K8 only, ACPI_NUMA. Tested on EM64T NUMA. Also tested with numa=off, numa=fake, and running a kernel compiled with NUMA on a regular EM64 2 way SMP. Signed-off-by:
Alok N Kataria <alokk@calsoftinc.com> Signed-off-by:
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Andi Kleen authored
No functional changes. And remove one redundant prototype. Signed-off-by:
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Andi Kleen authored
Replacing the old home brewn __force_inline. Signed-off-by:
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Andi Kleen authored
Passing random input values in eax to cpuid is not a good idea because the CPU will GPF for unknown ones. Use the correct x86-64 version that exists for a longer time too. This also adds a memory barrier to prevent the optimizer from reordering. Cc: tigran@veritas.com Signed-off-by:
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Andi Kleen authored
RDTSC serialization using cpuid is not needed for Intel platforms. This increases gettimeofday performance. Cc: vojtech@suse.cz Cc: rohit.seth@intel.com Signed-off-by:
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Andi Kleen authored
The real vsyscall .text addresses are not mapped when the alternative() replacement runs early, so use some black magic to access them using the direct mapping. Signed-off-by:
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Andi Kleen authored
Needed for follow on patches Signed-off-by:
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Andi Kleen authored
They already do this in hardware and the Linux algorithm actually adds errors. Cc: mingo@elte.hu Cc: rohit.seth@intel.com Signed-off-by:
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Andi Kleen authored
cpumask.h wasn't included implicitely into proto.h in this case. Just move it over to smp.h Signed-off-by:
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Vivek Goyal authored
o Apic id is in most significant 8 bits of APIC_ID register. Current code is trying to write apic id to least significant 8 bits. This patch fixes it. o This fix enables booting uni kdump capture kernel on a cpu with non-zero apic id. Signed-off-by:
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Brian Gerst authored
Remove exports that are already exported from the object's source file. Signed-off-by:
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Brian Gerst authored
These functions are inlines and shouldn't be exported. Signed-off-by:
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Andi Kleen authored
This function is never used for x86_64. Signed-off-by:
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Andi Kleen authored
They are referred to often so avoid potential false sharing for them. Signed-off-by:
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Andi Kleen authored
As suggested by Linus. This catches driver bugs that could cause corruption on IOMMU architectures. Also I converted the BUGs to out_of_line_bug()s to save a bit of text space. Signed-off-by:
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Andi Kleen authored
Just add the missing PCI ID. Cc: perex@suse.cz Cc: tiwai@suse.de Signed-off-by:
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Andi Kleen authored
Hopefully the users will take the hint. Signed-off-by:
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Andi Kleen authored
- Remove optimization for old B stepping Opteron - Make the fast path for copies with a multiple of eight length faster. - Minor instruction rearrangement to hopefully avoid a pipeline stall or two. - Add comment about errata to consider. Signed-off-by:
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Muli Ben-Yehuda authored
AK: I hacked Muli's original patch a lot and there were a lot of changes - all bugs are probably to blame on me now. There were also some changes in the fall back behaviour for swiotlb - in particular it doesn't try to use GFP_DMA now anymore. Also all DMA mapping operations use the same core dma_alloc_coherent code with proper fallbacks now. And various other changes and cleanups. Known problems: iommu=force swiotlb=force together breaks needs more testing. This patch cleans up x86_64's DMA mapping dispatching code. Right now we have three possible IOMMU types: AGP GART, swiotlb and nommu, and in the future we will also have Xen's x86_64 swiotlb and other HW IOMMUs for x86_64. In order to support all of them cleanly, this patch: - introduces a struct dma_mapping_ops with function pointers for each of the DMA mapping operations of gart (AMD HW IOMMU), swiotlb (software IOMMU) and nommu (no IOMMU). - gets rid of: if (swiotlb) return swiotlb_xxx(); - PCI_DMA_BUS_IS_PHYS is now checked against the dma_ops being set This makes swiotlb faster by avoiding double copying in some cases. Signed-Off-By:Muli Ben-Yehuda <mulix@mulix.org> Signed-Off-By:
Jon D. Mason <jdmason@us.ibm.com> Signed-off-by:
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Andi Kleen authored
Broken BIOS on Iwill 8way systems reports these and it causes the bootmem allocator to crash. Add a sanity check if all the PXMs in the SRAT table cover all memory as reported by e820. If the sanity check fails the SRAT is rejected and the code will fall back to discover the NUMA topology using the K8 northbridge registers when applicable. Signed-off-by:
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Andi Kleen authored
This adds a new notifier chain that is called with IDLE_START when a CPU goes idle and IDLE_END when it goes out of idle. The context can be idle thread or interrupt context. Since we cannot rely on MONITOR/MWAIT existing the idle end check currently has to be done in all interrupt handlers. They were originally inspired by the similar s390 implementation. They have a variety of applications: - They will be needed for CONFIG_NO_IDLE_HZ - They can be used for oprofile to fix up the missing time in idle when performance counters don't tick. - They can be used for better C state management in ACPI - They could be used for microstate accounting. This is just infrastructure so far, no users. Signed-off-by:
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Andi Kleen authored
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Andi Kleen authored
No functional changes Signed-off-by:
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Andi Kleen authored
Fix off by one when checking if the machine has enougn memory to need IOMMU This caused the IOMMUs to be needlessly enabled for mem=4G Based on a patch from Jon Mason Signed-off-by: jdmason@us.ibm.com Signed-off-by:
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Venkatesh Pallipadi authored
Whenever we see that a CPU is capable of C3 (during ACPI cstate init), we disable local APIC timer and switch to using a broadcast from external timer interrupt (IRQ 0). Patch below adds the code for x86_64. Signed-off-by:
Venkatesh Pallipadi <venkatesh.pallipadi@intel.com> Signed-off-by:
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Venkatesh Pallipadi authored
Whenever we see that a CPU is capable of C3 (during ACPI cstate init), we disable local APIC timer and switch to using a broadcast from external timer interrupt (IRQ 0). This is needed because Intel CPUs stop the local APIC timer in C3. This is currently only enabled for Intel CPUs. Patch below adds the code for i386 and also the ACPI hunk. Signed-off-by:
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Venkatesh Pallipadi authored
Remove the finer control of local APIC timer. We cannot provide a sub-jiffy control like this when we use broadcast from external timer in place of local APIC. Instead of removing this only on systems that may end up using broadcast from external timer (due to C3), I am going the "I'm feeling lucky" way to remove this fully. Basically, I am not sure about usefulness of this code today. Few other architectures also don't seem to support this today. If you are using profiling and fine grained control and don't like this going away in normal case, yell at me right now. Signed-off-by:
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