- 01 Mar, 2010 5 commits
-
-
Sandeep Paulraj authored
The DM365 Spectrum Digital EVM comes with an EEPROM connected to SPI0. This patch adds support for the SPI EEPROM. Signed-off-by:
Sandeep Paulraj <s-paulraj@ti.com> Signed-off-by:
Kevin Hilman <khilman@deeprootsystems.com>
-
Sandeep Paulraj authored
This patch adds SPI init for DM365. It does the following 1) Initializes SPI0 2) Defines resources to be used by SPI0 3) Adds platform data for SPI0 Signed-off-by:
-
Sandeep Paulraj authored
This patch does the following 1) Minor change to the SPI clocks making it similar to DM365. 2) Changing the interrupt used by SPI0 3) Adding EDMA resources that can be used by SPI0 4) Adding platform specific data. Signed-off-by:
-
Sandeep Paulraj authored
This patch adds "spi.h" header file that will be used by board and architecture specific code. Signed-off-by:
-
Kevin Hilman authored
Remove unneeded 'struct davinci_clk' wrapper around 'struct clk_lookup' and use clk_lookup directly. Signed-off-by:
-
- 04 Feb, 2010 35 commits
-
-
Kevin Hilman authored
Remove unneeded 'struct davinci_clk' wrapper around 'struct clk_lookup' and use clkdev_add_table() to add the list of clocks in one go. Signed-off-by: -
Miguel Aguilar authored
This patch adds the generic Voice Codec support for the DM365 based platforms. Signed-off-by:
Miguel Aguilar <miguel.aguilar@ridgerun.com> Acked-by:
Mark Brown <broonie@opensource.wolfsonmicro.com> Signed-off-by:
-
Sekhar Nori authored
When supporting I2C/SPI based on-board PLLs like CDCE949, it is essential that clk->set_rate be able to sleep. Currently, this is not possible because clk->set_rate is called from within spin-lock in clk_set_rate This patch brings clk->set_rate outside of the spin-lock and lets the individual set_rate implementations achieve serialization through appropiate means. Signed-off-by:
Sekhar Nori <nsekhar@ti.com> Signed-off-by:
-
Philby John authored
Patch adds SDA and SCL pin numbers to the i2c platform data structure for Davinci DM355 and DM6446. This at present is used for i2c bus recovery. TODO: Add SDA and SCL pin number information to include all Davinci platforms such as dm355-leopard, dm365, dm646x, da8xx etc. Signed-off-by:
Philby John <pjohn@in.mvista.com> Signed-off-by:
-
Sudhakar Rajashekhara authored
Currently da850/omap-l138 supports only one channel controller instance of EDMA though EDMA driver as such supports multiple channel controller instances. This patch adds platform data for the 2nd EDMA channel controller. As, the platform data differ between da830/omap-l137 and da850/omap-l138, existing code has been re-shuffled to accommodate this. Signed-off-by:
Sudhakar Rajashekhara <sudhakar.raj@ti.com> Signed-off-by:
-
Sudhakar Rajashekhara authored
Currently, the edma_noevent list is passed from platform data. But on some architectures, there will be many EDMA channels which will not be used at all. This patch scans all the platform devices and then builds a list of events which are not being used. The unused event list will be used to allocate EDMA channels in case of EDMA_CHANNEL_ANY usage instead of the edma_noevent being used earlier for this purpose. This patch is based on David Brownells's suggestion at http://article.gmane.org/gmane.linux.davinci/15176. Signed-off-by:
-
Sudhakar Rajashekhara authored
Though edma_alloc_channel api was looping through the available channel controllers in EDMA_CHANNEL_ANY case, it was never returning the channel for 2nd channel controller, if 1st channel controller had no free channels. This issue has been fixed with this patch. Signed-off-by:
-
Sudhakar Rajashekhara authored
Some architectures have only one channel controller, but the edma_alloc_channel api loops twice to findout the free channel available in EDMA_CHANNEL_ANY case. A new variable has been introduced to keep count of number of channel controllers being used on a particular architecture. Signed-off-by:
-
Sudhakar Rajashekhara authored
Currently, edma_alloc_channel api is returning the channel number without prepending the controller on which the channel was allocated. So, if a channel is allocated on 2nd controller, calls subsequent to edma_alloc_channel would never know that channel was allocated on the 2nd controller, and continue to operate on 1st controller, resulting in edma failure. This patch fixes this issue. Signed-off-by:
-
Nageswari Srinivasan authored
This patch adds the CDCE949 reference oscillator to the davinci clock list. On the DM6467T EVM, the CDCE949 is responsible for generating the pixel clock for display. On the DM6467 EVM, this pixel clock was being obtained from an internal source. This is not possible on the DM6467T EVM because of the presence of a 33MHz oscillator. The TSIF module also requires the CDCE949 to generate the data clocks. The actual clock definitions will be added by patches adding support for DM6467T VPIF and TSIF. This patch mearly lays the foundation for that work. Signed-off-by:
Nageswari Srinivasan <nageswari@ti.com> Signed-off-by:
-
Nageswari Srinivasan authored
This patch adds support for TI's CDCE949 - a clock synthesizer with 4 PLLs and 9 outputs. It is used on DM6467 EVM. On the EVM, it generates clocks required for VPIF, TSIF and Audio modules. This patch adds it as part of the DaVinci clock framework. Testing: The various frequency outputs on Y1 have been tested using a out-of-tree VPIF video driver supporting HD video. The register values for Y5 frequency outputs have been derived from TSIF driver sources in MontaVista LSP kernel, but actual output has not been tested for lack of TSIF driver which actually works on the latest kernel. Signed-off-by:
-
Sekhar Nori authored
Signed-off-by:
-
Sekhar Nori authored
This patch adds support for registering for suspend-to-RAM functionality on da850/omap-l138 SoCs. da850 supports wakeup based on external event and RTC alarm. Currently only RTC alarm based wakeup is supported. Support for wakeup based on external event will be added as later improvements. For scheduling an alarm event on RTC some useful code is present in Documentation/rtc.txt Signed-off-by:
-
Sekhar Nori authored
This patch adds core power management (suspend-to-RAM) support for DaVinci SoCs. The code depends on the the "deepsleep" feature to suspend the SoC and saves power by gating the input clock. The wakeup can be based on an external event as supported by the SoC. Assembly code (in sleep.S) is added to aid gating DDR2 clocks. Code doing this work should not be accessing DDR2. The assembly code is relocated to SRAM by the code in pm.c The support has been validated on DA850/OMAP-L138 only though the code is (hopefully) generic enough that other SoCs supporting deepsleep feature simply requires SoC specific code to start using this driver. Note that all the device drivers don't support suspend/resume still and are being worked on. Signed-off-by:
-
Sandeep Paulraj authored
In DM365 Q0, Q1 and Q2 are used by codecs. LSP drivers should use Q3. This patch changes the default queue for DM365. Signed-off-by:
-
Chaithrika U S authored
Some modules do not have PSC to control their clocks. The 'lpsc' field in the clk structure is 0 for such clocks. In the clock disable function check for CLK PSC flag before disabling the PSC. If this is not taken care of then it may so happen that module controlled by LPSC 0 is erroneously disabled. Signed-off-by:
Chaithrika U S <chaithrika@ti.com> Signed-off-by:
-
Sriramakrishnan authored
When programming the DMA engine, the next pointers must be programmed with physical address as seen from the DMA master address space. This address may be different from physical address of the buffer RAM area. This patch abstracts the buffer address translation logic. Signed-off-by:
Sriramakrishnan <srk@ti.com> Acked-by:
David S. Miller <davem@davemloft.net> Signed-off-by:
-
Sriramakrishnan authored
On certain SOCs, the EMAC controller is interfaced with a wrapper logic for handling interrupts. This patch implements a platform specific hook to cater to platforms that require custom interrupt handling logic Signed-off-by:
-
Sriramakrishnan authored
The davinci EMAC peripheral is also available on other TI platforms -notably TI AM3517 SoC. This patch modifies the config option and the platform structure header files so that the driver can be reused on non-davinci platforms as well. Signed-off-by:
-
Sudhakar Rajashekhara authored
This patch initializes the platform data to enable 4-bit ecc support on DA850/OMAP-L138. Signed-off-by:
-
Sudhakar Rajashekhara authored
On DA850/OMAP-L138, NOR flash partition was starting from offset ZERO erasing the UBL and u-boot when the complete NOR is erased. This patch moves the start of the partition to 512K, after the bootloaders and u-boot env variables. This patch also creates a new partition on NOR Flash to store Linux kernel image. Signed-off-by:
-
Sekhar Nori authored
Move /proc/davinci_clocks to /sys/kernel/debug/davinci_clocks (debugfs). debugfs is more suited for this since the clock dump is debug information. Signed-off-by:
-
Sekhar Nori authored
This patch modifies clock dump to take care of clock tress rooted at multiple oscillators. Current code assumes the entire tree is rooted on a single oscillator. When using off-chip clock synthesizers, some of the clocks can be obtained from a different on-board oscillator. Signed-off-by:
-
Sekhar Nori authored
DM6467T (T for Turbo) is a newer and faster DM6467 part from TI. The new part supports 1080p video and has the ARM running at 495MHz. More SoC information: http://focus.ti.com/docs/prod/folders/print/tms320dm6467t.html Spectrum Digital, Inc has a new EVM for this part. It is _mostly_ same as the older DM6467 EVM except for a 33MHz crystal input and THS8200 video encoder for 1080p support. The meat of this patch is dedicated to initializing the crystal frequency from EVM board file. Additional notes: I did consider some alternative ways to make the crystal input board specific including - (1) having board code initialize the crystal frequency using the first member of soc_info->cpu_clks array (2) introducing a new ref_clk_rate member in soc_info structure. But, the current way seems to be the simplest and least intruding considering that both the clock array and SoC info structure are actually private to the SoC file. Also the fact that davinci_common_init() initializes both the soc_info and clocks in one go. Signed-off-by:
-
Sekhar Nori authored
Currently all the #defines and static variables in the board-dm646x-evm.c file are located right at the start of the file because of which the related code is not together - making reading the code difficult. This patch moves around the code keeping related code together. Signed-off-by:
-
Sekhar Nori authored
Leave a comment explaining the constant value of 27Mhz used in include/mach/timex.h for all DaVinci platforms. Many of the platforms actually run at 24MHz timer frequency (Eg. EVMs of DM355, DM365 and OMAP-L1). The comment also serves as a porting alert. Signed-off-by:
-
Sekhar Nori authored
Create static map for internal SRAM and populate SRAM base and size in soc_info structure to allow SRAM allocation functions from arch/arm/mach-davinci/sram.c to work. On DA850 SRAM is used for suspend-to-RAM implementation in places where DDR2 cannot be accessed as its clocks are stopped. Signed-off-by:
-
Sekhar Nori authored
On omap-l1 devices the PLL registers can be locked from writes. Currently the cpufreq rate setting code unlocks PLL0 before the write actually happens. With suspend support getting added PLL1 registers need be be unlocked as well. To facilitate this, unlock both PLLs during the init time itself. This also obviates the need to unlock PLL registers for each CPUFreq transtition. Signed-off-by:
-
Sekhar Nori authored
When suspend is supported, both cpuidle and suspend code need to work on DDR2 registers. Instead of mapping the DDR2 registers twice, do it once outside of cpuidle driver and let cpuidle driver get the virtual base address of DDR2 registers. Signed-off-by:
-
Sekhar Nori authored
psc.h contains register defines for PSC module which need to be accessed in assembly code which helps the DA850/OMAP-L138 SoC go to sleep. Shutting down DDR clock using PSC is a part of the sleep procedure. Also, the PLL related hardware definitions in clock.h are needed in assembly code to bypass the DDR2 PLL. Signed-off-by:
-
Sekhar Nori authored
The motivation behind the change is to use the same definitions in the assembly code responsible for suspending the SoC, a part of which is to clock gate the DDR2 clock. Note that the assembly code cannot invoke the C function meant for this. The main reason being that stack in DDR2 cannot be accessed while DDR2 clock is being clock gated. Signed-off-by:
-
Sekhar Nori authored
Move defintions of DDR2 controller registers to memory.h from cpuidle.c. The motivation behind the change is to be able to use these defintions in assembly code that puts DDR2 in self-refresh and enables the SoC to enter suspend state. Signed-off-by:
-
Sekhar Nori authored
As suspend support is added, the code supporting the suspend operation needs to bypass PLLs and needs to access the same wait time values as the PLL code in clock.c. To facilitate this, move the PLL wait times to clock.h where they can be accessed by suspend code. Signed-off-by:
-
Sekhar Nori authored
OMAP-L138 adds a second SYSCFG region having useful functionality like deep sleep, pull up/down control and SATA clock stop. This patch makes provision for accessing registers from second SYSCFG region in da8xx code. Note that OMAP-L137 has a single SYSCFG region. Signed-off-by:
-
Murali Karicheri authored
This patch adds following changes:- 1) add sub device configuration data for TVP5146 used by vpfe capture 2) registers platform devices for vpfe_capture, isif and vpss 3) defines hardware resources for the devices listed under 2) 4) defines clock aliase for isif driver 5) adding setup_pinmux() for isif Signed-off-by:
Murali Karicheri <m-karicheri2@ti.com> Signed-off-by:
-
