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  1. 03 Dec, 2008 1 commit
    • Grazvydas Ignotas's avatar
      ASoC: TWL4030: Add input selection and gain controls · 5920b453
      Grazvydas Ignotas authored 
      The TWL4030 codec device has two ADCs. Both of them can have
several inputs routed to them, but TRM says that only one source
can be selected for every ADC, even though every source has a
dedicated bit in the registers.

This patch adds input source controls. It modifies default register
values to have no inputs selected and ADCs disabled. When some
input is selected, control handlers enable apropriate input
amplifier and ADC. If a microphone is selected, bias power is
automatically enabled. When some input is deselected, unused
chip parts are disabled.

Microphone and line input recording tested on OMAP3 pandora board.
Signed-off-by: default avatarGrazvydas Ignotas <notasas@gmail.com>
Signed-off-by: default avatarMark Brown <broonie@opensource.wolfsonmicro.com>
      5920b453
  3. 02 Dec, 2008 2 commits
  5. 01 Dec, 2008 33 commits
  7. 30 Nov, 2008 4 commits
    • Paul Mackerras's avatar
      powerpc: Fix system calls on Cell entered with XER.SO=1 · ab598b66
      Paul Mackerras authored 
      It turns out that on Cell, on a kernel with CONFIG_VIRT_CPU_ACCOUNTING
= y, if a program sets the SO (summary overflow) bit in the XER and
then does a system call, the SO bit in CR0 will be set on return
regardless of whether the system call detected an error.  Since CR0.SO
is used as the error indication from the system call, this means that
all system calls appear to fail.

The reason is that the workaround for the timebase bug on Cell uses a
compare instruction.  With CONFIG_VIRT_CPU_ACCOUNTING = y, the
ACCOUNT_CPU_USER_ENTRY macro reads the timebase, so we end up doing a
compare instruction, which copies XER.SO to CR0.SO.  Since we were
doing this in the system call entry patch after clearing CR0.SO but
before saving the CR, this meant that the saved CR image had CR0.SO
set if XER.SO was set on entry.

This fixes it by moving the clearing of CR0.SO to after the
ACCOUNT_CPU_USER_ENTRY call in the system call entry path.
Signed-off-by: default avatarPaul Mackerras <paulus@samba.org>
Acked-by: default avatarArnd Bergmann <arnd@arndb.de>
Acked-by: default avatarBenjamin Herrenschmidt <benh@kernel.crashing.org>
      ab598b66
    • Arnd Bergmann's avatar
      powerpc/cell: Fix GDB watchpoints, again · 960cedb4
      Arnd Bergmann authored 
      An earlier patch from Jens Osterkamp attempted to fix GDB
watchpoints by enabling the DABRX register at boot time.
Unfortunately, this did not work on SMP setups, where
secondary CPUs were still using the power-on DABRX value.

This introduces the same change for secondary CPUs on cell
as well.
Reported-by: default avatarUlrich Weigand <Ulrich.Weigand@de.ibm.com>
Tested-by: default avatarUlrich Weigand <Ulrich.Weigand@de.ibm.com>
Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
Signed-off-by: default avatarPaul Mackerras <paulus@samba.org>
      960cedb4
    • Arnd Bergmann's avatar
      powerpc/mpic: Don't reset affinity for secondary MPIC on boot · cc353c30
      Arnd Bergmann authored 
      Kexec/kdump currently fails on the IBM QS2x blades when the kexec happens
on a CPU other than the initial boot CPU.  It turns out that this is the
result of mpic_init trying to set affinity of each interrupt vector to the
current boot CPU.

As far as I can tell,  the same problem is likely to exist on any
secondary MPIC, because they have to deliver interrupts to the first
output all the time. There are two potential solutions for this: either
not set up affinity at all for secondary MPICs, or assume that a single
CPU output is connected to the upstream interrupt controller and hardcode
affinity to that per architecture.

This patch implements the second approach, defaulting to the first output.
Currently, all known secondary MPICs are routed to their upstream port
using the first destination, so we hardcode that.
Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
Signed-off-by: default avatarPaul Mackerras <paulus@samba.org>
      cc353c30
    • Arnd Bergmann's avatar
      powerpc/cell/axon-msi: Retry on missing interrupt · d015fe99
      Arnd Bergmann authored 
      The MSI capture logic for the axon bridge can sometimes
lose interrupts in case of high DMA and interrupt load,
when it signals an MSI interrupt to the MPIC interrupt
controller while we are already handling another MSI.

Each MSI vector gets written into a FIFO buffer in main
memory using DMA, and that DMA access is normally flushed
by the actual interrupt packet on the IOIF.  An MMIO
register in the MSIC holds the position of the last
entry in the FIFO buffer that was written.  However,
reading that position does not flush the DMA, so that
we can observe stale data in the buffer.

In a stress test, we have observed the DMA to arrive
up to 14 microseconds after reading the register.

This patch works around this problem by retrying the
access to the FIFO buffer.

We can reliably detect the conditioning by writing
an invalid MSI vector into the FIFO buffer after
reading from it, assuming that all MSIs we get
are valid.  After detecting an invalid MSI vector,
we udelay(1) in the interrupt cascade for up to
100 times before giving up.
Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
Signed-off-by: default avatarPaul Mackerras <paulus@samba.org>
      d015fe99