1. 05 Nov, 2008 12 commits
    • Benjamin Herrenschmidt's avatar
      powerpc/pci: Use common PHB resource hookup · 53280323
      Benjamin Herrenschmidt authored
      The 32-bit and 64-bit powerpc PCI code used to set up the resource
      pointers of the root bus of a given PHB in completely different
      places.
      
      This unifies this in large part, by making 32-bit use a routine very
      similar to what 64-bit does when initially scanning the PCI busses.
      
      The actual setup of the PHB resources itself is then moved to a
      common function in pci-common.c.
      
      This should cause no functional change on 64-bit.  On 32-bit, the
      effect is that the PHB resources are going to be setup a bit earlier,
      instead of being setup from pcibios_fixup_bus().
      Signed-off-by: default avatarBenjamin Herrenschmidt <benh@kernel.crashing.org>
      Signed-off-by: default avatarPaul Mackerras <paulus@samba.org>
      53280323
    • Benjamin Herrenschmidt's avatar
      powerpc/pci: Cleanup debug printk's · b0494bc8
      Benjamin Herrenschmidt authored
      This removes the various DBG() macro from the powerpc PCI code and
      makes it use the standard pr_debug instead.
      Signed-off-by: default avatarBenjamin Herrenschmidt <benh@kernel.crashing.org>
      Signed-off-by: default avatarPaul Mackerras <paulus@samba.org>
      b0494bc8
    • Mark Nelson's avatar
      powerpc: Update 64bit memcpy() using CPU_FTR_UNALIGNED_LD_STD · 25d6e2d7
      Mark Nelson authored
      Update memcpy() to add two new feature sections: one for aligning the
      destination before copying and one for copying using aligned load
      and store doubles.
      
      These new feature sections will only affect Power6 and Cell because
      the CPU feature bit was only added to these two processors.
      
      Power6 gets its best performance in memcpy() when aligning neither the
      source nor the destination, while Cell gets its best performance when
      just the destination is aligned. But in order to save on CPU feature
      bits we can use the previously added CPU_FTR_CP_USE_DCBTZ feature bit
      to differentiate between Power6 and Cell (because CPU_FTR_CP_USE_DCBTZ
      was added to Cell but not Power6).
      
      The first feature section acts to nop out the branch that takes us to
      the code that aligns us to an eight byte boundary for the destination.
      We only want to nop out this branch on Power6.
      
      So the ALT_FTR_SECTION_END() for this feature section creates a test
      mask of the two feature bits ORed together and provides an expected
      result of just CPU_FTR_UNALIGNED_LD_STD, thus we nop out the branch
      if we're on a CPU that has CPU_FTR_UNALIGNED_LD_STD set and
      CPU_FTR_CP_USE_DCBTZ unset.
      
      For the second feature section added, if we're on a CPU that has the
      CPU_FTR_UNALIGNED_LD_STD bit set then we don't want to do the copy
      with aligned loads and stores (and the appropriate shifting left and
      right instructions), so we want to nop out the branch to
      .Lsrc_unaligned.
      
      The andi. used for this branch is moved to just above the branch
      because this allows us to nop out both instructions with just one
      feature section which gives us better performance and doesn't hurt
      readability which two separate feature sections did.
      
      Moving the andi. to just above the branch doesn't have any noticeable
      negative effect on the remaining 64bit processors (the ones that
      didn't have this feature bit added).
      
      On Cell this simple modification results in an improvement to measured
      memcpy() bandwidth of up to 50% in the hot cache case and up to 15% in
      the cold cache case.
      
      On Power6 we get memory bandwidth results that are up to three times
      faster in the hot cache case and up to 50% faster in the cold cache
      case.
      
      Commit 2a929436 ("powerpc: Add new CPU
      feature: CPU_FTR_CP_USE_DCBTZ") was where CPU_FTR_CP_USE_DCBTZ was
      added.
      
      To say that Cell gets its best performance in memcpy() with just the
      destination aligned is true but only for the reason that the indirect
      shift and rotate instructions, sld and srd, are microcoded on Cell.
      This means that either the destination or the source can be aligned,
      but not both, and seeing as we get better performance with the
      destination aligned we choose this option.
      
      While we're at it make a one line change from cmpldi r1,... to
      cmpldi cr1,... for consistency.
      Signed-off-by: default avatarMark Nelson <markn@au1.ibm.com>
      Signed-off-by: default avatarPaul Mackerras <paulus@samba.org>
      25d6e2d7
    • Mark Nelson's avatar
      powerpc: Add new CPU feature: CPU_FTR_UNALIGNED_LD_STD · 4ec577a2
      Mark Nelson authored
      Add a new CPU feature bit, CPU_FTR_UNALIGNED_LD_STD, to be added
      to the 64bit powerpc chips that can do unaligned load double and
      store double without any performance hit.
      
      This is added to Power6 and Cell and will be used in the next commit
      to disable the code that gets the destination address aligned on
      those CPUs where doing that doesn't improve performance.
      Signed-off-by: default avatarMark Nelson <markn@au1.ibm.com>
      Signed-off-by: default avatarPaul Mackerras <paulus@samba.org>
      4ec577a2
    • Brian King's avatar
      powerpc: Update page-in counter for CMM · 40900194
      Brian King authored
      A new field has been added to the VPA as a method for the client OS to
      communicate to firmware the number of page-ins it is performing when
      running collaborative memory overcommit.  The hypervisor will use this
      information to better determine if a partition is experiencing memory
      pressure and needs more memory allocated to it.
      Signed-off-by: default avatarBrian King <brking@linux.vnet.ibm.com>
      Signed-off-by: default avatarPaul Mackerras <paulus@samba.org>
      40900194
    • Sebastien Dugue's avatar
      powerpc/pseries: Fix getting the server number size · 1ef8014d
      Sebastien Dugue authored
      The 'ibm,interrupt-server#-size' properties are not in the cpu nodes,
      which is where we currently look for them, but rather live under the
      interrupt source controller nodes (which have "ibm,ppc-xics" in their
      compatible property).
      
      This moves the code that looks for the ibm,interrupt-server#-size
      properties from xics_update_irq_servers() into xics_init_IRQ().
      
      Also this adds a check for mismatched sizes across the interrupt
      source controller nodes.  Not sure this is necessary as in this case
      the firmware might be seriously busted.
      
      This property only appears on POWER6 boxes and is only used in the
      set-indicator(gqirm) call, and apparently firmware currently ignores
      the value we pass.  Nevertheless we need to fix it in case future
      firmware versions use it.
      Signed-off-by: default avatarSebastien Dugue <sebastien.dugue@bull.net>
      Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
      Acked-by: default avatarMilton Miller <miltonm@bga.com>
      Signed-off-by: default avatarPaul Mackerras <paulus@samba.org>
      1ef8014d
    • Anton Vorontsov's avatar
      powerpc: Remove device_type = "rtc" properties in .dts files · 691de576
      Anton Vorontsov authored
      We don't want to encourage the device_type usage.  It isn't used in
      the code, so we can simply remove it from the dts files.
      Suggested-by: default avatarScott Wood <scottwood@freescale.com>
      Signed-off-by: default avatarAnton Vorontsov <avorontsov@ru.mvista.com>
      Acked-by: default avatarGrant Likely <grant.likely@secretlab.ca>
      Acked-by: default avatarDavid Gibson <david@gibson.dropbear.id.au>
      Signed-off-by: default avatarPaul Mackerras <paulus@samba.org>
      691de576
    • Benjamin Herrenschmidt's avatar
      powerpc: Silence software timebase sync · a6a8e009
      Benjamin Herrenschmidt authored
      When no hardware method is provided to sync the timebase registers
      across the machine, and the platform doesn't sync them for us, then we
      use a generic software implementation.  Currently, the code for that
      has many printks, and they don't have log levels.  Most of the printks
      are only useful for debugging the code, and since we haven't had any
      problems with it for years, this turns them into pr_debug.
      Signed-off-by: default avatarBenjamin Herrenschmidt <benh@kernel.crashing.org>
      Signed-off-by: default avatarPaul Mackerras <paulus@samba.org>
      a6a8e009
    • Benjamin Herrenschmidt's avatar
      powerpc: Fix domain numbers in /proc on 64-bit · 1fd0f525
      Benjamin Herrenschmidt authored
      The code to properly expose domain numbers in /proc is somewhat
      bogus on ppc64 as it depends on the "buid" field being non-0,
      but that field is really pseries specific.
      
      This removes that code and makes ppc64 use the same code as 32-bit
      which effectively decides whether to expose domains based on
      ppc_pci_flags set by the platform, and sets the default for 64-bit
      to enable domains and enable compatibility for domain 0 (which
      strips the domain number for domain 0 to help with X servers).
      Signed-off-by: default avatarBenjamin Herrenschmidt <benh@kernel.crashing.org>
      Signed-off-by: default avatarPaul Mackerras <paulus@samba.org>
      1fd0f525
    • Stephen Rothwell's avatar
      powerpc: Fix "unused variable" warning in pci_dlpar.c · 454666eb
      Stephen Rothwell authored
      This gets rid of this build warning:
      
      arch/powerpc/platforms/pseries/pci_dlpar.c: In function 'init_phb_dynamic':
      arch/powerpc/platforms/pseries/pci_dlpar.c:192: warning: unused variable 'b'
      
      This is one of the very few warnings left in a ppc64_defconfig build and
      getting rid of it will make it easier to see future introduced ones (in
      fact this was introduced very recently).
      Signed-off-by: default avatarStephen Rothwell <sfr@canb.auug.org.au>
      Signed-off-by: default avatarPaul Mackerras <paulus@samba.org>
      454666eb
    • Alexey Dobriyan's avatar
      powerpc/cell: Fix compile error in ras.c · 9c8b4aff
      Alexey Dobriyan authored
      This fixes this error on Cell when CONFIG_KEXEC = n:
      
      arch/powerpc/platforms/cell/ras.c:299: error: implicit declaration of function 'crash_shutdown_register'
      
      We have to include <asm/kexec.h> because it contains the dummy
      definition of crash_shutdown_register that is used when
      CONFIG_KEXEC=n, but <linux/kexec.h> doesn't include <asm/kexec.h> in
      that case.
      Signed-off-by: default avatarAlexey Dobriyan <adobriyan@gmail.com>
      Signed-off-by: default avatarPaul Mackerras <paulus@samba.org>
      9c8b4aff
    • Alexey Dobriyan's avatar
      powerpc/ps3: Fix compile error in ps3-lpm.c · fce4d583
      Alexey Dobriyan authored
      Compiling with CONFIG_SMP = n and CONFIG_PS3_LPM != n gives this error:
      
      drivers/ps3/ps3-lpm.c:838: error: implicit declaration of function 'get_hard_smp_processor_id'
      
      This fixes it.  We have to include <asm/smp.h> rather than
      <linux/smp.h> because the UP definition of get_hard_smp_processor_id()
      is in <asm/smp.h>, and <linux/smp.h> only includes <asm/smp.h> if
      CONFIG_SMP = y.
      Signed-off-by: default avatarAlexey Dobriyan <adobriyan@gmail.com>
      Acked-by: default avatarGeoff Levand <geoffrey.levand@am.sony.com>
      Signed-off-by: default avatarPaul Mackerras <paulus@samba.org>
      fce4d583
  2. 04 Nov, 2008 15 commits
  3. 03 Nov, 2008 13 commits