- 09 Mar, 2010 40 commits
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Barry Song authored
Some IRQ handlers need to disable a DMA channel without waiting. Signed-off-by:
Barry Song <barry.song@analog.com> Signed-off-by:
Mike Frysinger <vapier@gentoo.org>
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Mike Frysinger authored
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Mike Frysinger authored
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Mike Frysinger authored
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Barry Song authored
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Graf Yang authored
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Graf Yang <graf.yang@analog.com> Signed-off-by:
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Barry Song authored
Restore support for CONFIG_EXCPT_IRQ_SYSC_L1 in the MPU CPLB manager. Signed-off-by:
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Barry Song authored
Rather than declaring pin resources in the drivers, do it in the board. Signed-off-by:
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Barry Song authored
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Michael Hennerich authored
This makes room for off-chip IRQ controllers. Signed-off-by:
Michael Hennerich <michael.hennerich@analog.com> Signed-off-by:
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Barry Song authored
Some userspace applications use this member in diagnosing crashes. It also makes some LTP tests pass (i.e. the Blackfin arch behaves more like everyone else). Signed-off-by:
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Mike Frysinger authored
Just generate a random MAC on the demo board since the ADF702x lacks dedicated storage for such things. Signed-off-by: -
Yi Li authored
Signed-off-by:
Yi Li <yi.li@analog.com> Signed-off-by:
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Harald Krapfenbauer authored
Signed-off-by:
Harald Krapfenbauer <harald.krapfenbauer@bluetechnix.at> Signed-off-by:
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Barry Song authored
When the kernel is executing out of parallel flash (XIP), we can't have the flash go into an erase/programming cycle, otherwise the instruction fetching steps fail and everything crashes. Signed-off-by:
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Cliff Cai authored
Signed-off-by:
Cliff Cai <cliff.cai@analog.com> Signed-off-by:
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Graf Yang authored
The locking code in the address dumper needs to grab the mm's mmap_sem so that other CPUs do not get an inconsistent view. On UP systems this really wasn't a problem, but it is easy to trigger a race on SMP systems when another CPU removes a mapping. Signed-off-by:
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Barry Song authored
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Mike Frysinger authored
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Roel Kluin authored
This condition allowed only decoding of opcode 0x0040 Signed-off-by:
Roel Kluin <roel.kluin@gmail.com> Signed-off-by:
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Barry Song authored
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Barry Song authored
During very early init, the stack pointer is given a slightly incorrect value (&init_thread_union). The value is later adjusted to the right one during early init (&init_thread_union + THREAD_SIZE), but it is used a few times in between. While the few functions used don't actually put things onto the stack (due to optimization), it's best if we simply use the right value from the start. Signed-off-by:
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Barry Song authored
Use the common attribute rather than setting the section name directly. The common linker script defines expect the newer naming. Signed-off-by:
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Barry Song authored
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Jie Zhang authored
Since we are now discarding .exit.text at runtime instead of link time, we need to place all .text sections ahead of the .data sections. Otherwise, a really large attached initramfs may cause link errors as it pushes the PC relative relocations behind the limits of the Blackfin ISA (~16meg). The instructions in the .exit.text are unable to call back into the .text sections leading to a link failure. Signed-off-by:
Jie Zhang <jie.zhang@analog.com> Signed-off-by:
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Yi Li authored
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Yi Li authored
There is no need to use {get,put}_cpu() when we already have a spinlock to protect against multiple processors running simultaneously. Signed-off-by: -
Graf Yang authored
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Yi Li authored
SMP systems require per-cpu local clock event devices in order to enable HRT support. One a BF561, we can use local core timer for this purpose. Originally, there was one global core-timer clock event device set up for core A. To accomplish this feat, we need to split the gptimer0/core timer logic so that each is a standalone clock event. There is no requirement that we only have one clock event source anyways. Once we have this, we just define per-cpu clock event devices for each local core timer. Signed-off-by:
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Graf Yang authored
Common API already provides functions for managing online CPUs. Signed-off-by:
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Sonic Zhang authored
Now that the Blackfin IRQ controller supports this, drivers get the normal functionality of controlling which CPU to bind IRQs to. Signed-off-by:
Sonic Zhang <sonic.zhang@analog.com> Signed-off-by:
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Mike Frysinger authored
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Mike Frysinger authored
Don't want the compiler assuming the rare sanity checks are the norm and optimize for those paths. Signed-off-by: -
Sonic Zhang authored
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Michael Hennerich authored
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Valentin Yakovenkov authored
Signed-off-by:
Valentin Yakovenkov <yakovenkov@gmail.com> Signed-off-by:
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Sonic Zhang authored
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Mike Frysinger authored
The Kconfig option was never mainlined, so replace the define with the actual pin that it is hooked up to by default. Signed-off-by: -
Mike Frysinger authored
These platforms don't hook up to this USB controller, so no point in declaring resources for it. Signed-off-by: -
Michael Hennerich authored
The BF51x's Instruction SRAM is 32kB, not 48kB. Signed-off-by:
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