- 04 Jun, 2009 1 commit
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Magnus Damm authored
This patch fixes the 16-bit case of the sh4a specific unaligned access implementation. Without this patch the 16-bit version of sh4a get_unaligned() results in a 32-bit read which may read more data than intended and/or cross page boundaries. Unbreaks mtd NOR write handling on Migo-R. Signed-off-by:
Magnus Damm <damm@igel.co.jp> Signed-off-by:
Paul Mundt <lethal@linux-sh.org>
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- 02 Jun, 2009 6 commits
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Kuninori Morimoto authored
Signed-off-by:
Kuninori Morimoto <morimoto.kuninori@renesas.com> Signed-off-by:
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Kuninori Morimoto authored
Signed-off-by:
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Kuninori Morimoto authored
Signed-off-by:
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Kuninori Morimoto authored
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SUGIOKA Toshinobu authored
Fix SCI transmission sequence in console output function. This reorders the write sequence to match the SH-3 manual, and corrects a console corruption bug observed on SH-3 SCI. Signed-off-by:
Toshinobu Sugioka <sugioka@itonet.co.jp> Signed-off-by:
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Kuninori Morimoto authored
CONFIG_SH_PCLK_FREQ=33333333 is correct for sh7724. sh7724 master clock is 33333333, but peripheral is 41666666. This bug came to light because sh-sci driver had changed clk from "module_clk" to "peripheral_clk" Signed-off-by:
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- 01 Jun, 2009 11 commits
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Paul Mundt authored
This tidies up the boot_cpu_data.flags probing on SH-4A. All of them have a few things in common, which we can blindly set, rather than having each subtype have to set the same flags. We can also make assumptions about cache ways and the validity of PTEA, so this also kills off CPU_HAS_PTEA as a config option. There was also a bug in the FPU probing, which is now tidied up. Signed-off-by: -
Paul Mundt authored
This tidies up the L2 probing, as it may or may not be implemented on a CPU, regardless of whether it is supported. This converts the cvr validity checks from BUG_ON()'s to simply clearing the CPU_HAS_L2_CACHE flag and moving on with life. Signed-off-by: -
Magnus Damm authored
Hook up the shared 4-bit divisor clock code to sh7785. Signed-off-by:
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Magnus Damm authored
Add shared code for 4-bit divisor clocks. Processor specific code can use SH_CLK_DIV4() to initialize div4 clocks, and then use sh_clk_div4_register() for registration. Signed-off-by:
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Magnus Damm authored
Hook up the shared 32-bit module stop bit code to sh7785. Signed-off-by:
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Magnus Damm authored
Add shared 32-bit module stop bit clock support. Processor specific code can use SH_CLK_MSTP32() to initialize module stop bit clocks, and then use sh_clk_mstp32() for registration. Signed-off-by:
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Kuninori Morimoto authored
Add the CPU_HAS_L2_CACHE flag to SH7724. Signed-off-by:
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Magnus Damm authored
This patch modifies the sh7785 clock code to use the MODE4 value to switch between 72x and 36x PLL multiplication. Signed-off-by:
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Magnus Damm authored
This patch adds mode pin support to the sh7785lcr board. The harware allows the user to control the mode pins using dip switches S1 and S2, but from the software the pins are fixed to the factory default since we have no way to reading out this configuration from software. Signed-off-by:
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Magnus Damm authored
This patch adds sh7785 mode pin definitions. Mode pins and pin function controller comments are added as well. Signed-off-by:
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Magnus Damm authored
Add mode pin support for the SuperH architecture V2. With this patch applied the board code can add their own function to export the cpu mode pin configuration. In most cases this will be a constant bitmap, but boards that allow reading this from a register can instead read out the pin state from hardware. The code warns if a pin is tested but no board specific mode pin function has been provided. Signed-off-by:
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- 26 May, 2009 12 commits
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Paul Mundt authored
This fixes a build error where references to pci_cache_line_size are undefined, as this ceases to be exported when PCI_DISABLE_MWI is enabled, as is now the default. Signed-off-by: -
Paul Mundt authored
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Paul Mundt authored
None of the SH PCI controllers support MWI, it is always treated as a direct memory write, so simply disable it outright. In the case of the PCI cache line size, consult that for the pci_dma_burst_advice() strategy, and switch over to PCI_DMA_BURST_MULTIPLE, as PPC64. Signed-off-by: -
Paul Mundt authored
As there is only a single controller and remapping has no impact for the address range in question, just initialize it directly in the controller definition. This fixes up boot time warnings about not having the field initialized. Signed-off-by: -
Paul Mundt authored
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Magnus Damm authored
This patch removes the ->build_rate_table() callback, ->recalc() may instead be used for this purpose. Signed-off-by:
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Magnus Damm authored
This patch converts the sh7785 clock code to make use of clk_rate_table_build() and clk_rate_table_round(). The ->build_rate_table() callback is removed, the table building is instead handled in ->recalc(). Signed-off-by:
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Magnus Damm authored
Add SuperH-specific clock framework helper functions: - clk_rate_table_build() - build cpufreq table from divisors/multipliers - clk_rate_table_round() - use cpufreq table to find matching frequency Signed-off-by:
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Magnus Damm authored
This patch converts the sh7785 pll implementation from the all-in-one code in frqmr_recalc() and frqmr_build_rate_table() to a separate struct clk. This allows us to remove the processor specific multiplier and use generic rate table functions. Signed-off-by:
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Paul Mundt authored
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Kuninori Morimoto authored
This adds preliminary support for the ms7724se solution engine board. Signed-off-by:
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Paul Mundt authored
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- 22 May, 2009 8 commits
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Paul Mundt authored
This kills off after_bootmem and switches to using slab_is_available() instead. Presently the only place this is used is by the sh64 ioremap, and there's not much point in keeping the reference around otherwise. Signed-off-by: -
Paul Mundt authored
This adds a new SH_CLK_CPG for parts that have CPG support. SH_CLK_CPG_LEGACY is made to depend on this, and still needs to be set for platforms that want clock-cpg to register the legacy clocks. With this new config item in place, it is now possible to start layering more generic CPG code in place while other platforms transition off of the legacy clocks. Signed-off-by: -
Paul Mundt authored
This adds a NR_IRQS_LEGACY definition, which will be used by sparse irq. Signed-off-by: -
Paul Mundt authored
irq_to_desc_alloc_cpu() has been renamed to irq_to_desc_alloc_node() in -next, but as we can not presently enable SPARSE_IRQ without the early irq_desc alloc patch, protect it with an ifdef until the interface has settled and we are ready to enable it system-wide. Signed-off-by: -
Paul Mundt authored
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Magnus Damm authored
This patch fixes the LCDC driver to avoid calling the function sh_mobile_lcdc_start_stop(priv, 0) unless the same function has been called before to start the LCDC hardware. Triggered when sh_mobile_lcdcfb.c failed to probe() due to missing MSTP clocks. Signed-off-by:
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Magnus Damm authored
This patch fixes the ap325rxa ncm03j camera code to handle the case where no i2c driver is present. Without this fix i2c_transfer() may be passed NULL as adapter which results in a crash. Triggered when i2c-sh_mobile.c failed to probe() due to missing MSTP clocks. Signed-off-by:
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Roel Kluin authored
Do not go beyond ARRAY_SIZE of onchip_ops Signed-off-by:
Roel Kluin <roel.kluin@gmail.com> Signed-off-by:
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- 21 May, 2009 2 commits
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Magnus Damm authored
Fix clkfwk branch compile error in clock-sh7722.c. Signed-off-by:
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Paul Mundt authored
This is just a simple arch_probe_nr_irqs() stub that wraps to the platform defined number of IRQs. This can be made gradually more intelligent based on what we can infer from the INTC tables and so on. Signed-off-by:
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