- 17 Apr, 2008 40 commits
-
-
Alexey Starikovskiy authored
Signed-off-by:
Alexey Starikovskiy <astarikovskiy@suse.de> Signed-off-by:
Ingo Molnar <mingo@elte.hu>
-
Alexey Starikovskiy authored
Signed-off-by:
-
Alexey Starikovskiy authored
Signed-off-by:
-
Ingo Molnar authored
Signed-off-by: -
Alexey Starikovskiy authored
Signed-off-by:
-
Alexey Starikovskiy authored
Signed-off-by:
-
Ingo Molnar authored
Signed-off-by: -
Alexey Starikovskiy authored
Signed-off-by:
-
Alexey Starikovskiy authored
Signed-off-by:
-
Ingo Molnar authored
Signed-off-by: -
Alexey Starikovskiy authored
Signed-off-by:
-
Alexey Starikovskiy authored
Signed-off-by:
-
Alexey Starikovskiy authored
Signed-off-by:
-
Alexey Starikovskiy authored
Signed-off-by:
-
Alexey Starikovskiy authored
Signed-off-by:
-
Alexey Starikovskiy authored
Signed-off-by:
-
Alexey Starikovskiy authored
Signed-off-by:
-
Alexey Starikovskiy authored
Signed-off-by:
-
Alexey Starikovskiy authored
Signed-off-by:
-
Arjan van de Ven authored
The new cacheflush.h API's didn't have any comments describing how they're to be used yet and the conventions around these functions. This patch adds comments to this effect; in order for that to be a logical series, some prototypes had to move around. Signed-off-by:
Arjan van de Ven <arjan@linux.intel.com> Signed-off-by:
-
Dave Jones authored
Upcoming 64 bit processors from Centaur can use sysenter. Signed-off-by:
Dave Jones <davej@codemonkey.org.uk> Signed-off-by:
Jesse Ahrens <jahrens@centtech.com> Signed-off-by:
-
Jeremy Fitzhardinge authored
Using a naked parameterless macro could lead to other tokens being unexpectedly replaced. Signed-off-by:
Jeremy Fitzhardinge <jeremy.fitzhardinge@citrix.com> Signed-off-by:
-
Jesper Juhl authored
When compilers became generally better at optimizing code than humans, the register keyword became mostly useless. For the floppy driver it certainly is since it's so slow compared to the rest of the system that optimizing access to a single variable or two isn't going to make any real difference So let's just leave it to the compiler - it'll do a better job anyway. This patch does away with a few register keywords in the x86 floppy driver. Signed-off-by:
Jesper Juhl <jesper.juhl@gmail.com> Signed-off-by:
-
Glauber Costa authored
take them out of the x86_64-specific asm/mach_apic.h Signed-off-by:
Glauber Costa <gcosta@redhat.com> Signed-off-by:
-
Cyrill Gorcunov authored
By including processor-flags.h we are allowed to use predefined macroses instead of keeping own ones Signed-off-by:
Cyrill Gorcunov <gorcunov@gmail.com> Signed-off-by:
-
Ingo Molnar authored
Signed-off-by: -
Glauber Costa authored
take them out of the x86_64-only asm/mach_apic.h Signed-off-by:
-
Andi Kleen authored
On AMD SMM protected memory is part of the address map, but handled internally like an MTRR. That leads to large pages getting split internally which has some performance implications. Check for the AMD TSEG MSR and split the large page mapping on that area explicitely if it is part of the direct mapping. There is also SMM ASEG, but it is in the first 1MB and already covered by the earlier split first page patch. Idea for this came from an earlier patch by Andreas Herrmann On a RevF dual Socket Opteron system kernbench shows a clear improvement from this: (together with the earlier patches in this series, especially the split first 2MB patch) [lower is better] no split stddev split stddev delta Elapsed Time 87.146 (0.727516) 84.296 (1.09098) -3.2% User Time 274.537 (4.05226) 273.692 (3.34344) -0.3% System Time 34.907 (0.42492) 34.508 (0.26832) -1.1% Percent CPU 322.5 (38.3007) 326.5 (44.5128) +1.2% => About 3.2% improvement in elapsed time for kernbench. With GB pages on AMD Fam1h the impact of splitting is much higher of course, since it would split two full GB pages (together with the first 1MB split patch) instead of two 2MB pages. I could not benchmark a clear difference in kernbench on gbpages, so I kept it disabled for that case That was only limited benchmarking of course, so if someone was interested in running more tests for the gbpages case that could be revisited (contributions welcome) I didn't bother implementing this for 32bit because it is very unlikely the 32bit lowmem mapping overlaps into the TSEG near 4GB and the 2MB low split is already handled for both. [ mingo@elte.hu: do it on gbpages kernels too, there's no clear reason why it shouldnt help there. ] Signed-off-by:Andi Kleen <ak@suse.de> Acked-by: andreas.herrmann3@amd.com Cc: mingo@elte.hu Signed-off-by:
Thomas Gleixner <tglx@linutronix.de> Signed-off-by:
-
Andi Kleen authored
RDMSR for 64bit values with exception handling. Makes it easier to deal with 64bit valued MSRs. The old 64bit code base had that too as checking_rdmsrl(), but it got dropped somehow. Signed-off-by:
Andi Kleen <andi@firstfloor.org> Cc: andreas.herrmann3@amd.com Cc: mingo@elte.hu Signed-off-by:
-
Andi Kleen authored
Intel recommends to not use large pages for the first 1MB of the physical memory because there are fixed size MTRRs there which cause splitups in the TLBs. On AMD doing so is also a good idea. The implementation is a little different between 32bit and 64bit. On 32bit I just taught the initial page table set up about this because it was very simple to do. This also has the advantage that the risk of a prefetch ever seeing the page even if it only exists for a short time is minimized. On 64bit that is not quite possible, so use set_memory_4k() a little later (in check_bugs) instead. Signed-off-by:
-
Andi Kleen authored
Add a new function to force split large pages into 4k pages. This is needed for some followup optimizations. I had to add a new field to cpa_data to pass down the information that try_preserve_large_page should not run. Right now no set_page_4k() because I didn't need it and all the specialized users I have in mind would be more comfortable with pure addresses. I also didn't export it because it's unlikely external code needs it. Signed-off-by:
-
Andi Kleen authored
When end_pfn is not aligned to 2MB (or 1GB) then the kernel might map more memory than end_pfn. Account this in max_pfn_mapped. Signed-off-by:
-
Thomas Gleixner authored
Signed-off-by:
-
Andi Kleen authored
Even on 32bit 2MB pages can map more memory than is in the true max_low_pfn if end_pfn is not highmem and not aligned to 2MB. Add a end_pfn_map similar to x86-64 that accounts for this fact. This is important for code that really needs to know about all mapping aliases. Signed-off-by:
-
Andi Kleen authored
Currently they are in .text.head because the rest of head_64.S. .text.head is not removed as init data, but the early exception handlers should be because they are not needed after early boot of the BP. So move them over. Signed-off-by:
-
Andi Kleen authored
The early exception handlers are currently set up using a macro recursion. There is only one user left. Replace the macro with a standard loop in place. Noop patch, just a cleanup. [ tglx@linutronix.de: simplified ] Signed-off-by:
-
Andi Kleen authored
All of early setup runs with interrupts disabled, so there is no need to set up early exception handlers for vectors >= 32 This saves some minor text size. Signed-off-by:
-
gorcunov@gmail.com authored
Signed-off-by:
-
gorcunov@gmail.com authored
Signed-off-by:
-
gorcunov@gmail.com authored
Signed-off-by:
-
