- 02 Mar, 2010 1 commit
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Márton Németh authored
The id_table field of the struct pci_driver is constant in <linux/pci.h> so it is worth to make initialization data also constant. The semantic match that finds this kind of pattern is as follows: (http://coccinelle.lip6.fr/) // <smpl> @r@ disable decl_init,const_decl_init; identifier I1, I2, x; @@ struct I1 { ... const struct I2 *x; ... }; @s@ identifier r.I1, y; identifier r.x, E; @@ struct I1 y = { .x = E, }; @c@ identifier r.I2; identifier s.E; @@ const struct I2 E[] = ... ; @depends on !c@ identifier r.I2; identifier s.E; @@ + const struct I2 E[] = ...; // </smpl> Signed-off-by:
Márton Németh <nm127@freemail.hu> Cc: Julia Lawall <julia@diku.dk> Signed-off-by:
Jean Delvare <khali@linux-fr.org>
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- 01 Mar, 2010 39 commits
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Linus Torvalds authored
Merge branch 'davinci-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-davinci * 'davinci-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-davinci: (40 commits) DaVinci DM365: Adding support for SPI EEPROM DaVinci DM365: Adding DM365 SPI support DaVinci DM355: Modifications to DM355 SPI support DaVinci: SPI: Adding header file for SPI support. davinci: dm646x: CDCE clocks: davinci_clk converted to clk_lookup davinci: clkdev cleanup: remove clk_lookup wrapper, use clkdev_add_table() DaVinci: DM365: Voice codec support for the DM365 SoC davinci: clock: let clk->set_rate function sleep Add SDA and SCL pin numbers to i2c platform data davinci: da8xx/omap-l1xx: Add EDMA platform data for da850/omap-l138 davinci: build list of unused EDMA events dynamically davinci: Fix edma_alloc_channel api for EDMA_CHANNEL_ANY case davinci: Keep count of channel controllers on a platform davinci: Correct return value of edma_alloc_channel api davinci: add CDCE949 support on DM6467 EVM davinci: add support for CDCE949 clock synthesizer davinci: da850/omap-l138 EVM: register for suspend support davinci: da850/omap-l138: add support for SoC suspend davinci: add power management support DaVinci: DM365: Changing default queue for DM365. ...
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git://git.kernel.org/pub/scm/linux/kernel/git/jgarzik/libata-devLinus Torvalds authored
* 'upstream-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jgarzik/libata-dev: (38 commits) sata_via: Delay on vt6420 when starting ATAPI DMA write ata: Detect Delkin Devices compact flash pata_efar: Enable parallel scanning pata_atiixp: enable parallel scan [libata] pata_atiixp: add locking for parallel scanning [libata] pata_efar: add locking for parallel scanning libata: Pass host flags into the pci helper [libata] pata_marvell: CONFIG_AHCI is really CONFIG_SATA_AHCI libata: Allow pata_legacy to be built on non-ISA but PCI systems pata_pdc202xx_old: fix UDMA mode for PDC2026x chipsets pata_pdc202xx_old: fix UDMA mode for Promise UDMA33 cards [libata] pata_at91: fix backslash-continued string pata_via: store UDMA masks in via_isa_bridges table pata_via: fix address setup timings underlocking pata_serverworks: fix error message pata_serverworks: fix PIO setup for the second channel pata_efar: fix secondary port support pata_cypress: fix PIO timings underclocking pata_cs5535: use correct values for PIO1 and PIO2 data timings pata_cmd64x: remove unused definitions ...
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Bart Hartgers authored
When writing a disc on certain lite-on dvd-writers (also rebadged as optiarc/LG/...) connected to a vt6420, the ATAPI CDB ends up in the datastream and on the disc, causing silent corruption. Delaying between sending the CDB and starting DMA seems to prevent this. I do not know if there are burners that do not suffer from this, but the patch should be safe for those as well. There are many reports of this issue, but AFAICT no solution was found before. For example: http://lkml.indiana.edu/hypermail/linux/kernel/0802.3/0561.htmlSigned-off-by:
Bart Hartgers <bart.hartgers@gmail.com> Signed-off-by:
Jeff Garzik <jgarzik@redhat.com>
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Ben Gardner authored
I have a Delkin Devices compact flash card that isn't being recognized using the SATA/PATA drivers. The card is recognized and works with the deprecated ATA drivers. The error I am seeing is: ata1.00: failed to IDENTIFY (device reports invalid type, err_mask=0x0) I tracked it down to ata_id_is_cfa() in include/linux/ata.h. The Delkin card has id[0] set to 0x844a and id[83] set to 0. This isn't what the kernel expects and is probably incorrect. The simplest work-around is to add a check for 0x844a to ata_id_is_cfa(). Signed-off-by:
Ben Gardner <gardner.ben@gmail.com> Signed-off-by:
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Alan Cox authored
Again originally proposed by Bartlomiej but this does it by using the generic helper logic instead. Signed-off-by:
Alan Cox <alan@linux.intel.com> Signed-off-by:
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Alan Cox authored
This was originally proposed by Bartlomiej but as a device specific expansion of the init_one function rather than making the helper more generic. Enable the parallel scan via the generic flags. Signed-off-by:
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Bartlomiej Zolnierkiewicz authored
This is similar change as commit 60c3be38 for ata_piix host driver and while pata_atiixp doesn't enable parallel scan yet the race could probably also be triggered by requesting re-scanning of both ports at the same time using SCSI sysfs interface. [Ported to current tree without other patch dependancies by Alan Cox] Original is Signed-off-by:
Bartlomiej Zolnierkiewicz <bzolnier@gmail.com> This one is Signed-off-by:
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Bartlomiej Zolnierkiewicz authored
Add clearing of UDMA enable bit also for PIO modes and then add extra locking for parallel scanning. This is similar change as commit 60c3be38 for ata_piix host driver and while pata_efar doesn't enable parallel scan yet the race could probably also be triggered by requesting re-scanning of both ports at the same time using SCSI sysfs interface. [Ported to current kernel without other patch dependancies by Alan Cox] Original is Signed-off-by:
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Alan Cox authored
This allows parallel scan and the like to be set without having to stop using the existing full helper functions. This patch merely adds the argument and fixes up the callers. It doesn't undo the special cases already in the tree or add any new parallel callers. Signed-off-by:
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Christoph Egger authored
The marvell driver comtains a fallback to ahci for the sata ports which is incorrectly checked as CONFIG_AHCI while the only AHCI config item is actually called SATA_AHCI (which also sounds sensible considering it's a fallback for the sata ports). Signed-off-by:
Christoph Egger <siccegge@stud.informatik.uni-erlangen.de> Signed-off-by:
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Alan Cox authored
This is needed for some unsupported hardware setups on strange 64bit mainboards where crazy stuff has been done like putting flash ata adapters on the LPC bus, or where the real hardware is hidden/confused. Signed-off-by:
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Bartlomiej Zolnierkiewicz authored
PDC2026x chipsets need the same treatment as PDC20246 one. This is completely untested but will hopefully fix UDMA issues that people have been reporting against pata_pdc202xx_old for the last couple of years. Signed-off-by:
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Bartlomiej Zolnierkiewicz authored
On Monday 04 January 2010 02:30:24 pm Russell King wrote: > Found the problem - getting rid of the read of the alt status register > after the command has been written fixes the UDMA CRC errors on write: > > @@ -676,7 +676,8 @@ void ata_sff_exec_command(struct ata_port *ap, const struct > ata_taskfile *tf) > DPRINTK("ata%u: cmd 0x%X\n", ap->print_id, tf->command); > > iowrite8(tf->command, ap->ioaddr.command_addr); > - ata_sff_pause(ap); > + ndelay(400); > +// ata_sff_pause(ap); > } > EXPORT_SYMBOL_GPL(ata_sff_exec_command); > > > This rather makes sense. The PDC20247 handles the UDMA part of the > protocol. It has no way to tell the PDC20246 to wait while it suspends > UDMA, so that a normal register access can take place - the 246 ploughs > on with the register access without any regard to the state of the 247. > > If the drive immediately starts the UDMA protocol after a write to the > command register (as it probably will for the DMA WRITE command), then > we'll be accessing the taskfile in the middle of the UDMA setup, which > can't be good. It's certainly a violation of the ATA specs. Fix it by adding custom ->sff_exec_command method for UDMA33 chipsets. Debugged-by:Russell King <rmk@arm.linux.org.uk> Signed-off-by:
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Jeff Garzik authored
Noticed and rough patch by Joe Perches. Signed-off-by: -
Bartlomiej Zolnierkiewicz authored
* store UDMA masks in via_isa_bridges[] and while at it make "flags" field to be u8 instead of u16 * convert the driver to use UDMA masks from via_isa_bridges[] * remove no longer needed VIA_UDMA* defines Make some minor documentation and CodingStyle fixes while at it. Signed-off-by:
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Bartlomiej Zolnierkiewicz authored
Correct via_do_set_mode() documentation while at it. Signed-off-by:
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Bartlomiej Zolnierkiewicz authored
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Bartlomiej Zolnierkiewicz authored
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Bartlomiej Zolnierkiewicz authored
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Bartlomiej Zolnierkiewicz authored
Timing registers should be programmed with the desired number of clocks minus one clock. Signed-off-by:
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Bartlomiej Zolnierkiewicz authored
There shouldn't be any problems with it as IDE cs5535 host driver has been using those values for years and they match values given in the (publicly available) datasheet. Signed-off-by:
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Bartlomiej Zolnierkiewicz authored
s/ARTIM2/ARTTIM23/ in cmd648_bmdma_stop() while at it Signed-off-by:
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Bartlomiej Zolnierkiewicz authored
Clear the primary channel pending interrupt bit instead of the reserved one. Signed-off-by:
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Bartlomiej Zolnierkiewicz authored
Account for the requirements of the DMA mode currently used by the pair device. Signed-off-by:
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Bartlomiej Zolnierkiewicz authored
Fix incorrect handling of recovery clocks value == 16 resulting in overclocked recovery timings & potentially underclocked active timings. Signed-off-by:
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Bartlomiej Zolnierkiewicz authored
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Bartlomiej Zolnierkiewicz authored
Use standard cycle timing for CFA PIO5 and PIO6 modes. Based on commit 74638c84 for IDE subsystem. Signed-off-by:
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Bart Hartgers authored
Before only the timings for master were set. Datasheet can be found here: ftp://ftp.vtbridge.org/Docs/Storage/DS_VT6421A_100_CCPL.PDF Surprisingly, a slave drive works without this patch. According to the datasheet, the controller by default derives the DMA mode from the Set Features command issued to a drive. Not sure about the PIO timings, though. The real problem is that the timings for the master effectively are the ones tuned for the slave. If these support different UDMA-settings, there is trouble, especially when the slave supports a higher UDMA than the master. Anyhow, using the same mechanism for both master and slave seems like a good idea. Signed-off-by:
Tejun Heo <tj@kernel.org> Signed-off-by:
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Robert Hancock authored
Make some variables in ahci and a function in pata_pcmcia static, as found using sparse. Signed-off-by:
Robert Hancock <hancockrwd@gmail.com> Signed-off-by:
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Tejun Heo authored
Traditional IDE interface sucks in that it doesn't have a reliable IRQ pending bit, so if the controller raises IRQ while the driver is expecting it not to, the IRQ won't be cleared and eventually the IRQ line will be killed by interrupt subsystem. Some controllers have non-standard mechanism to indicate IRQ pending so that this condition can be detected and worked around. This patch adds an optional operation ->sff_irq_check() which will be called for each port from the ata_sff_interrupt() if an unexpected interrupt is received. If the operation returns %true, ->sff_check_status() and ->sff_irq_clear() will be cleared for the port. Note that this doesn't mark the interrupt as handled so it won't prevent IRQ subsystem from killing the IRQ if this mechanism fails to clear the spurious IRQ. This patch also implements ->sff_irq_check() for ata_piix. Note that this adds slight overhead to shared IRQ operation as IRQs which are destined for other controllers will trigger extra register accesses to check whether IDE interrupt is pending but this solves rare screaming IRQ cases and for some curious reason also helps weird BIOS related glitch on Samsung n130 as reported in bko#14314. http://bugzilla.kernel.org/show_bug.cgi?id=14314 * piix_base_ops dropped as suggested by Sergei. * Spurious IRQ detection doesn't kick in anymore if polling qc is in progress. This provides less protection but some controllers have possible data corruption issues if the wrong register is accessed while a command is in progress. Signed-off-by:
Johannes Stezenbach <js@sig21.net> Reported-by:
Hans Werner <hwerner4@gmx.de> Cc: Alan Cox <alan@lxorguk.ukuu.org.uk> Cc: Sergei Shtylyov <sshtylyov@ru.mvista.com> Signed-off-by:
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Tejun Heo authored
host->ports[i] is never NULL if i < host->n_ports and non-NULL return from ata_qc_from_tag() guarantees that the returned qc is active. Drop unnecessary tests. Superflous () dropped as suggested by Sergei. Signed-off-by:
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Seth Heasley authored
Signed-off-by:
Seth Heasley <seth.heasley@intel.com> Signed-off-by:
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Seth Heasley authored
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Shane Huang authored
Tested on AMD internal reference board. Signed-off-by:
Shane Huang <shane.huang@amd.com> Acked-by:
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Sergei Shtylyov authored
HPT36x chips just don't have DPLL. Signed-off-by:
Sergei Shtylyov <sshtylyov@ru.mvista.com> Signed-off-by:
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Sergei Shtylyov authored
Describe UDMA timing bits 18-20 and 21 separately; add a note to bit 31 about it being meaningful for PIO only. Reformat the whole comment, while at it... Signed-off-by:
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Sergei Shtylyov authored
There's no need to clear the fast interrupt bit in hpt366_set_mode() since we're doing it in hpt366_init_chipset() already. While at it, rename 'addr1' local variable to 'addr' and exclude 'ap->port_no' from its calculation as HPT36x are single-channel-per-function chips. Signed-off-by:
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Sergei Shtylyov authored
As these drivers' set_piomode() and set_dmamode() methods are almost identical, factor out the common hpt{37x|3x2n}_set_mode() function to be called by both of them, the same as in 'pata_hpt366' driver. This results in ~5% decrease in the 'pata_hpt37x' driver binary size and in ~4% decrease in the 'pata_hpt3x2n' driver binary size (as measured on x86-32). Signed-off-by: -
Sergei Shtylyov authored
The UltraDMA Tss timing must be stretched with ATA clock of 66 MHz, but the driver only does this when PCI clock is 66 MHz, whereas it always programs DPLL clock (which is used as the ATA clock) to 66 MHz. Signed-off-by:
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