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- 25 Jan, 2008 1 commit
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Paul Walmsley authored
On the OMAP3430 architecture, some clocks are only available on 3430ES1 (e.g., the GFX subsystem, and the 16.8MHz input crystal rate option) and some clocks are only available on 3430ES2 (e.g., DPLL5, temp sensor, etc.) Now that OMAP3430ES revision detection is in the tree, we can flag these so we do not try to initialize clocks that don't exist on other ES revisions. To do so, add new clock flags CLOCK_IN_OMAP3430ES1 and CLOCK_IN_OMAP3430ES2, to be used for clocks that only exist on one architecture or the other. CLOCK_IN_OMAP343X is still present and used for clocks which exist on all 343X-level devices. The current code assumes that production clocks will be identical to 3430ES2 clocks, but this is easy enough to change if necessary. Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
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- 28 Sep, 2007 1 commit
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Paul Walmsley authored
Define the clock tree, and add basic supporting clock code, for the OMAP34xx chips. The definitions and code go into two new files, clock34xx.[ch]. The 34xx clock tree and code is written to reuse as much of the existing OMAP clock infrastructure as is reasonable, and to introduce the minimum amount possible of special-case code. One notable addition is the expansion of the dpll_params structure to include the additional DPLL control registers used on OMAP34XX; most of these extra registers are used in subsequent patches. The patches seek to follow the TRM closely. One implication of this is that several intermediary clocks are defined that are not software-controllable, and could normally be removed. Some examples include omap_96m_fck, core_l3_ick, corex2_fck. I included these clocks for several reasons. Any further changes in pre-production OMAP34xx silicon revisions may cause one of these clocks to become software-controllable; the extra clocks make it easier to double-check this patch against the TRM, if anyone wishes to do so; and ultimately, it is easier to remove these clocks than to add them back in. I anticipate that we will remove these intermediary clocks once the 3430 silicon and clock definitions mature. There are some notable divergences between the TRM and the patch. They include: * Clock suffixes end in "ck" rather than "clk"; this follows OMAP2 clock naming style to minimize driver changes in the rest of the tree. * The dpll*_alwon_fck clocks have been removed (they are not software controllable, and are unlikely to change) * Some documentation in the TRM is inconsistent; I sought to apply the most likely resolution in the code. Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
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- 25 May, 2007 1 commit
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Paul Walmsley authored
Add symbolic constants for Clock Management register bits for the OMAP3430 architecture. Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
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