- 25 Sep, 2008 1 commit
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Tony Lindgren authored
Clean-up i2c-omap Signed-off-by:Tony Lindgren <tony@atomide.com>
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- 24 Sep, 2008 7 commits
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Tony Lindgren authored
Big MMC init clean up: - Remove enabled field from slots. It is really intended to mean enabled controller, not enabled slot. Some controllers can have multiple multiplexed slots connected to the first controller, such as H4 and N8X0. - Initialize MMC devices dynamically as suggested by Russell King - Fix omap1 mmc clock instance numbers - Also attempt to fix massive omap1 MMC breakage caused by patch 138ab9f8. Remove obviously broken MMC configurations for now. MMC is still not working for any omap1 boards. Signed-off-by:
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Tony Lindgren authored
This fixes booting, and is a step toward fixing things properly: - Make enable_reg u32 instead of u16 - Get rid of VIRTUAL_IO_ADDRESS for clocks - Use __raw_read/write instead of omap_read/write for clock registers This patch adds a bunch of compile warnings until omap1 clock also uses offsets. Signed-off-by: -
Uwe Kleine-König authored
Don't use __init but __devinit to define probe function. A pointer to omap_mcbsp_probe is passed to the core via platform_driver_register and so the function must not disappear when the init code is freed. Using __init and having HOTPLUG=y the following probably oopses: echo -n omap-mcbsp.1 > /sys/bus/platform/driver/omap-mcbsp/unbind echo -n omap-mcbsp.1 > /sys/bus/platform/driver/omap-mcbsp/bind While at it move the remove function to the .devexit.text section. Signed-off-by:
Uwe Kleine-König <ukleinek@strlen.de> Cc: Russell King <rmk+kernel@arm.linux.org.uk> Cc: Tony Lindgren <tony@atomide.com> Signed-off-by:
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Jarkko Nikula authored
Without RX and TX interrupt definitions, the omap_mcbsp_request will fail on OMAP2430 and OMAP34xx for ports 3-5 since default io_type is OMAP_MCBSP_IRQ_IO. Signed-off-by:
Jarkko Nikula <jarkko.nikula@nokia.com> Signed-off-by:
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Jarkko Nikula authored
Bootloader may let McBSP logic running so make sure that block is idle before requesting IRQs. Also make sure that TX and RX waitqueues are initialized before request_irq. Signed-off-by:
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Tony Lindgren authored
This reverts commit 3fa3f8c8. Some regs are offsets for omap2/3. Signed-off-by:
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Tony Lindgren authored
This got broken because of mismerge from arm-devel. Signed-off-by:
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- 23 Sep, 2008 10 commits
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Tony Lindgren authored
Fix compile for twl4030-power Signed-off-by: -
Felipe Balbi authored
Trivial cleanup patch. Signed-off-by:
Felipe Balbi <felipe.balbi@nokia.com> Signed-off-by:
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Felipe Balbi authored
convert to use ioremap() and __raw_{read/write} friends. Signed-off-by:George G. Davis <gdavis@mvista.com> Signed-off-by:
Wim Van Sebroeck <wim@iguana.be> Signed-off-by:
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Felipe Balbi authored
Some changes to omap_wdt.c were lost due to, probably, mis-merges and developers working separately on linux-omap and mainline. Signed-off-by:
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arun c authored
without this the below error messages were coming continuously TWL4030 module irq 369 is disabled but can't be masked! <2>TWL4030 module irq 369 is disabled but can't be masked! Signed-off-by:
Arun C <arunedarath@mistralsolutions.com> Acked-by:
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Peter 'p2' De Schrijver authored
Signed-off-by:
Peter 'p2' De Schrijver <peter.de-schrijver@nokia.com> Signed-off-by:
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Steve Sakoman authored
Overo was omitted from the changes in 74fcfe9c This patch brings Overo RTC setup into line with the other omap boards Signed-off-by:
Steve Sakoman <steve@sakoman.com> Signed-off-by:
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David Brownell authored
For boards with twl4030/tps65950 chips, update board setup code to provide the appropriate board info. This should evolve a bunch more over time; right now too much of this data is globally defined (like IRQ and GPIO numbering). Signed-off-by:
David Brownell <dbrownell@users.sourceforge.net> Signed-off-by:
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David Brownell authored
More updates preparing for upstream merge of twl4030 driver: Basic fixes - twl4030-core becomes a new-style I2C driver - declare and use platform_data structure for that core - stop hard-wiring the irq numbers - check functionality that's really used: I2C, not SMBus Cleanup: - remove needless "client string" - remove some fake "bool" types - include catalog part numbers (TPS659{5,3,2}0) - diagnostics should identify the driver! To use this, all boards with these chips will need to declare this chip when they declare their active I2C busses (done in a separate patch). NOTE: the TWL4030_IRQ_* symbols still need to vanish, along with other global resource assignments associated with these chips. Signed-off-by: -
Madhusudhan Chikkature authored
Signed-off-by: Madhusudhan Chikkature<madhu.cr@ti.com> Signed-off-by:
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- 22 Sep, 2008 22 commits
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Paul Walmsley authored
Add in some missing IRQs for secure peripherals, defined in OMAP34xx Multimedia High Security Device Silicon Revision 3.0 Security Addendum Version B (SWPU119B) Signed-off-by:
Paul Walmsley <paul@pwsan.com> Signed-off-by:
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Paul Walmsley authored
This patch adds the register definitions and clock tree fields required to wait for the USIM module to come out of idle when the USIM clocks are enabled. Register bit definitions are from the 34xx HS Addendum Rev B. There, the clock is in fact named "USIM_ICLK". Signed-off-by:
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Paul Walmsley authored
Simplify omap2_clk_wait_ready() to use the new idlest_bit field in struct clk, rather than the hunk of conditionals that were there previously. Signed-off-by:
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Paul Walmsley authored
For each OMAP module that has a target IDLEST bit, add the appropriate bits to the clock tree on both the module interface clock and the appropriate functional clock. Add a new clock bit, "WAIT_READY", that indicates that the clock code must wait for the clock's module to come out of idle after both the target functional clock and interface clocks are enabled. Fix some clock flag comments while there to indicate that clocks marked as "3430ES2" clocks also are valid for later 3430 revisions. Several OMAP3xxx clocks must be split into platform-specific variants, since some early silicon revisions do not have target idle state bits available. DSS, HSOTGUSB, and SSI clocks are affected. In the future, it would be ideal to #ifdef out those clocks for kernels that don't need to run on 3430ES1 chips to save memory. Signed-off-by:
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Paul Walmsley authored
Originally when the PRCM register macros were defined, bit shift macros used a "_SHIFT" suffix, and mask macros used none. This became a source of bugs and confusion, as the mask macros were mistakenly used for shift values. Gradually, the mask macros have been updated, piece by piece, to add a "_MASK" suffix on the end to clarify. This patch applies this change to the CM_IDLEST_* register bits. The patch also adds a few bits that were missing, mostly from the 3430ES1 to ES2 revisions. Signed-off-by:
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Paul Walmsley authored
This patch fixes a few OMAP2xxx CM_IDLEST bits that were incorrectly marked as being OMAP2xxx-wide, when they were actually 2420-specific. Signed-off-by:
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Paul Walmsley authored
Use the clk->prcm_mod field for all register addresses in struct clk. Remove all usage of the *_REGADDR() and *_OFFSET() macros from the clock tree. This eliminates a set of (__force void __iomem *) casts and removes all of the OMAP2xxx register address rewriting. Shrink the width of the enable_reg/clksel_reg registers to 16 bits, saving 4 bytes per struct clk. Signed-off-by:
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Paul Walmsley authored
Get rid of void __iomem * usage in omap2_clksel_get_src_field. Prepend the function name with an underscore to highlight that it is a static function. Signed-off-by:
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Paul Walmsley authored
Remove omap2_get_clksel() and just use clk->clksel_reg and clk->clksel_mask directly. Signed-off-by:
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Paul Walmsley authored
Convert omap2_wait_clock_ready() to use clk.prcm_mod rather than a void __iomem *. This removes some cruft from clock24xx.c and sets up further cruft removal in a subsequent patch. Signed-off-by:
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Paul Walmsley authored
Use the newly-added clk.prcm_mod field in omap2_clk_wait_ready(), removing some internal register arithmetic. Signed-off-by:
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Paul Walmsley authored
Convert the bare constants in the register arithmetic in omap2_clk_wait_ready() to use meaningful symbolic names. Signed-off-by:
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Paul Walmsley authored
Create new static functions to read/write registers used in the struct clk, _omap2_clk_{read,write}_reg(). A subsequent patch will use these to ensure the correct register read/write instruction is used, which depends on whether the clock registers are in the CM, PRM, or SCM. Signed-off-by: -
Paul Walmsley authored
Annotate each OMAP2xxx real hardware clock controlled by the PRCM with the PRCM module offset. A subsequent patch will use this to simplify register addressing in the struct clk. Signed-off-by:
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Paul Walmsley authored
Add a "prcm_mod" field to the struct clk in OMAP2/3, and annotate each OMAP2xxx real hardware clock controlled by the PRCM with the PRCM module offset. (A subsequent patch will annotate OMAP3 clocks.) Add flags for this field that allow the registers to be marked as existing in the PRM, CM, or System Control Module. A subsequent patch will use this to simplify register addressing in the struct clk. Signed-off-by:
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Paul Walmsley authored
Some unnecessarily verbose variable names are used in several clock.c functions; clean these up per CodingStyle. Signed-off-by:
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Paul Walmsley authored
McBSP clock source control registers are located in the System Control Module, not the PRCM. However, the clock enable/disable registers are in the CM. Since the following patches require all registers in a struct clk to be in only one of {CM, PRM, SCM}, we must split the source clock selection into a separate struct clk from the clock enable/disable control. Signed-off-by: -
Paul Walmsley authored
The DPLL's rate changes when it enters or leaves bypass, so the DPLL's rate and the rates of all dependent clocks need to be recalculated when this happens. Also, fix test for bypass to test against the appropriate bypass clock, rather than the parent clock (which is not the bypass clock for DPLL1 and DPLL2). Signed-off-by:
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Paul Walmsley authored
This patch causes a DPLL to enter bypass when it is instructed to set its rate to that of its bypass clock. Previously this was only possible after setting the DPLL rate, then disabling and re-enabling it. Signed-off-by:
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Paul Walmsley authored
Convert the DPLL bypass test in omap3_clkoutx2_recalc() to test DPLL IDLEST bits rather than the CM_CLKEN register. Signed-off-by:
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Paul Walmsley authored
Removes the clksel-based DPLL rate handling from the OMAP3 clock tree. In its place, omap2_get_dpll_rate() now has code to determine whether the DPLL is bypassed. This obsoletes several clocks, which are removed by this patch. Signed-off-by:
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Paul Walmsley authored
Most DPLLs use sys_clk as their bypass rate source. But DPLL1 and DPLL2 use high-frequency bypass clocks dpll1_fclk and dpll2_fclk as their parents during bypass. Add a new struct dpll_data field to track the DPLL's bypass source clock. Kevin Hilman <khilman@deeprootsystems.com> helped catch this - thanks Kevin. Signed-off-by:
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